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  1. Nov 10, 2018
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  3. Aug 08, 2017
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  6. Sep 27, 2016
  7. Dec 09, 2014
    • Peter Jansweijer's avatar
      genrams/xilinx: address bus modulo ram size but only for simulation · 12c045eb
      Peter Jansweijer authored and Grzegorz Daniluk's avatar Grzegorz Daniluk committed
      The simulator is crashing at the end of the LM32 startup code when it tries to
      access the highest RAM location (at the stack pointer). After this access, the
      LM32 verilog code already increments the address to be prepared for the next
      cycle, which will never actually happen because you are at the end of the RAM.
      It is this address increment in verilog that is one address outside the defined
      RAM array for which the simulator complains and terminates. The actual
      synthesized code is perfectly fine; no accesses outside RAM.
      12c045eb
  8. Mar 08, 2013
  9. Mar 05, 2013
    • Wesley W. Terpstra's avatar
      genram: add a "dont_care" option for g_addr_conflict_resolution · 7df80bd4
      Wesley W. Terpstra authored
      The RW ordering on address conflict varies by platform.
      Some platforms only support some options.
      Most of the dprams in WR are portable and don't depend on the order.
      This new option allows a core to specify that it does not care what
      the result of a RW conflict is, and thus work on more platforms.
      
      For Xilinx, "dont_care" = "read_first", the old default.
      7df80bd4
    • Wesley W. Terpstra's avatar
      genrams: remove init_value generic option · fb24703c
      Wesley W. Terpstra authored
      In the past we used a generic to set the initial memory contents on altera.
      Unfortunately, quartus compiles big generics slowly (read: hours).
      Now we can load from a .mif file instead, which is much faster (seconds).
      Thus, this old option is no longer needed.
      fb24703c
  10. Mar 28, 2012
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  18. May 02, 2011