Commits · 2f4143b070ba6603f2ccc9191c162b9417a5e6b5 · Projects / Platform-independent core collection · GitLab

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Nov 02, 2011
- genrams: wea_i/web_i must not be ignored in byte addressed mode · 2f4143b0
  Tomasz Wlostowski authored 13 years ago
  
  2f4143b0
- Refactor the variable names · 8f48feb3
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  8f48feb3
- It is now possible to much more clearly state how async and sync differ. · 60206e72
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  60206e72
- Remove all the special-case code dealing with errors. It was hard to reason about, timing-wise. · 8ec84d06
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Make the error device a completely standard wishbone device;
we don't need high performance segfaults. Clearer is better.

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  8ec84d06
- Detect when there is a bus error. · 6b340010
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  6b340010
- The stack was overflowing the size of the wired dp ram. · c91a49e4
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  c91a49e4
- The actual bugfix for registered crossbar timings. · 2d2f5265
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
This bug allowed a high priority master to seize control of a lower priority master if:
1. The low priority master had control for exactly one cycle
2. Combinatorial crossbar mode was off

... this made it possible to "steal the ACK" of another device and cause the bus to stall.

This commit will be followed by a few others which also tidy up the code a
bit in a way that would have made this bug more obvious to a reviewer.

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  2d2f5265
- depth != width. Overflow of integer size => register file uncleared. · 31538117
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  31538117
- It is much easier to trace the workings of the crossbar if you can see the granted pins! · 8b2dc1e3
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  8b2dc1e3
- xwb_simple_uart: must tie ERR, RTY & INT lines to zero when not used · 6934e72f
  Tomasz Wlostowski authored 13 years ago
  
  6934e72f
- Modelsim requires all wires explicitly declared. · 824a460b
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  824a460b
- updated lm32_testsys testbench · c8dc1989
  Tomasz Wlostowski authored 13 years ago
  
  c8dc1989
Nov 01, 2011
- genrams: removed extra delays on clock lines for simulation · 28382b30
  Tomasz Wlostowski authored 13 years ago
  
  28382b30
- genrams: disabled messages in memory_loader_pkg · 58959bc6
  Tomasz Wlostowski authored 13 years ago
  
  58959bc6
- wishbone/wb_lm32: re-generated verilog code · 3f661b88
  Tomasz Wlostowski authored 13 years ago
  
  3f661b88
- Add a local logarithm function to get it to compile under ISE. · 6c64ef61
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  6c64ef61
- When GSI replaced the lattice specific ram block with inferred memory, it... · aa10c197
  Wesley W. Terpstra authored 13 years ago and Tomasz Wlostowski committed 13 years ago
```
When GSI replaced the lattice specific ram block with inferred memory, it became impossible to clear the register file as described by the two deleted lines. It is also unnecessary as the ram block starts zeroed.

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
```
  aa10c197
- changed the CPU profile in the testbench to medium · 95f003bd
  Tomasz Wlostowski authored 13 years ago
  
  95f003bd
- added testbench for LM32 sample system · cb32156c
  Tomasz Wlostowski authored 13 years ago
  
  cb32156c
Oct 27, 2011
- testbench: added sample LM32 system · e151eb2a
  Tomasz Wlostowski authored 13 years ago
  
  e151eb2a
Oct 26, 2011
- wishbone: wb_lm32: fixed compilation errors · 912d51c6
  Tomasz Wlostowski authored 13 years ago
  
  912d51c6
Oct 25, 2011
- genrams: fixed bwsel size bug · 4f870cde
  Tomasz Wlostowski authored 13 years ago
  
  4f870cde
- updated .gitignore · da3adbd3
  Tomasz Wlostowski authored 13 years ago
  
  da3adbd3
Oct 05, 2011
- wishbone: updated components package and manifest with new components · 92aa04cb
  Tomasz Wlostowski authored 13 years ago
  
  92aa04cb
- wishbone: wb_spi: added WB slave adapter and xwb_ wrapper · f49e11f4
  Tomasz Wlostowski authored 13 years ago
  
  f49e11f4
- wishbone: wb_slave_adapter: now asserts STB until ACKed in classic mode · 898be73f
  Tomasz Wlostowski authored 13 years ago
  
  898be73f
- wishbone: wb_onewire_master: added WB slave adapter and xwb_ wrapper, updated copyright info · 05296b35
  Tomasz Wlostowski authored 13 years ago
  
  05296b35
- wishbone: wb_lm32: re-generated LM32 profiles · 4a81b9b6
  Tomasz Wlostowski authored 13 years ago
  
  4a81b9b6
- wishbone: wb_lm32: defaulted undefined/Hi-Z states on LM32 data busses to 0 to... · f66cf2d9
  Tomasz Wlostowski authored 13 years ago
```
wishbone: wb_lm32: defaulted undefined/Hi-Z states on LM32 data busses to 0 to avoid simulation hangs
```
  f66cf2d9
- wishbone: wb_i2c_master: added WB slave adapter and xwb_ wrapper · d115a4a1
  Tomasz Wlostowski authored 13 years ago
  
  d115a4a1
- wishbone: wb_gpio_port: added extra address bits to support more than 32 I/Os, fixed file headeR · a8c41f0e
  Tomasz Wlostowski authored 13 years ago
  
  a8c41f0e
- wishbone: xwb_bus_fanout: fixed ACK generation bug · 28ad4406
  Tomasz Wlostowski authored 13 years ago
  
  28ad4406
- wishbone: wb_tics: added structized wrapped and WB slave adapter · 8f8e451d
  Tomasz Wlostowski authored 13 years ago
  
  8f8e451d
- modules: wb_simple_uart: merged with wb_virtual_uart, added WB slave adapter · 1c2d9e2d
  Tomasz Wlostowski authored 13 years ago
  
  1c2d9e2d
- wishbone: wb_virtual_uart: removed separate VUART entity (now merged with the UART) · c85f5c17
  Tomasz Wlostowski authored 13 years ago
  
  c85f5c17
Oct 04, 2011
- genrams: new file loader (DPRAMs only) · 7f0fe3cd
  Tomasz Wlostowski authored 13 years ago
  
  7f0fe3cd
- wishbone: wb_conmax: removed module from the Manifest (no longer used, kept for legacy designs) · 23d59e20
  Tomasz Wlostowski authored 13 years ago
  
  23d59e20
- wishbone: xwb_lm32: added missing platform/top/JTAG files · eeb4824d
  Tomasz Wlostowski authored 13 years ago
  
  eeb4824d
- wishbone: wb_gpio_port: added classic/pipelined adapter · 7f0810a0
  Tomasz Wlostowski authored 13 years ago
  
  7f0810a0
- wb_async_bridge: bugfixes in slave adapter, added generc for CPU bus width · e39ded74
  Tomasz Wlostowski authored 13 years ago
  
  e39ded74