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Platform-independent core collection
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Platform-independent core collection
Commits
6c64ef61
Commit
6c64ef61
authored
13 years ago
by
Wesley W. Terpstra
Committed by
Tomasz Wlostowski
13 years ago
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Add a local logarithm function to get it to compile under ISE.
Signed-off-by:
Tomasz Wlostowski
<
tomasz.wlostowski@cern.ch
>
parent
aa10c197
No related merge requests found
Changes
1
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1 changed file
modules/wishbone/wb_onewire_master/sockit_owm.v
+11
-3
11 additions, 3 deletions
modules/wishbone/wb_onewire_master/sockit_owm.v
with
11 additions
and
3 deletions
modules/wishbone/wb_onewire_master/sockit_owm.v
+
11
−
3
View file @
6c64ef61
...
...
@@ -105,18 +105,26 @@ module sockit_owm #(
// local parameters
//////////////////////////////////////////////////////////////////////////////
function
integer
clogb2
;
input
[
31
:
0
]
value
;
begin
for
(
clogb2
=
0
;
value
>
0
;
clogb2
=
clogb2
+
1
)
value
=
value
>>
1
;
end
endfunction
// size of combined power and select registers
localparam
PDW
=
(
BDW
==
32
)
?
24
:
8
;
// size of boudrate generator counter (divider for normal mode is largest)
localparam
CDW
=
CDR_E
?
((
BDW
==
32
)
?
16
:
8
)
:
$
clog2
(
CDR_N
);
localparam
CDW
=
CDR_E
?
((
BDW
==
32
)
?
16
:
8
)
:
clog
b
2
(
CDR_N
);
// size of port select signal
localparam
SDW
=
$
clog2
(
OWN
);
localparam
SDW
=
clog
b
2
(
OWN
);
// size of cycle timing counter
localparam
TDW
=
(
T_RSTH_O
+
T_RSTL_O
)
>
(
T_RSTH_N
+
T_RSTL_N
)
?
$
clog2
(
T_RSTH_O
+
T_RSTL_O
)
:
$
clog2
(
T_RSTH_N
+
T_RSTL_N
);
?
clog
b
2
(
T_RSTH_O
+
T_RSTL_O
)
:
clog
b
2
(
T_RSTH_N
+
T_RSTL_N
);
//////////////////////////////////////////////////////////////////////////////
// local signals
...
...
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