testbench: added sample LM32 system

testbench/wishbone/lm32_testsys/lm32_test_system.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+entity lm32_test_system is
+  
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    gpio_b    : inout std_logic_vector(31 downto 0);
+    onewire_b : inout std_logic;
+    txd_o     : out   std_logic;
+    rxd_i     : in    std_logic
+    );
+
+end lm32_test_system;
+
+architecture rtl of lm32_test_system is  
+  constant c_cnx_slave_ports  : integer := 2;
+  constant c_cnx_master_ports : integer := 3;
+
+  constant c_peripherals : integer := 3;
+
+
+  signal cnx_slave_in  : t_wishbone_slave_in_array(c_cnx_slave_ports-1 downto 0);
+  signal cnx_slave_out : t_wishbone_slave_out_array(c_cnx_slave_ports-1 downto 0);
+
+  signal cnx_master_in  : t_wishbone_master_in_array(c_cnx_master_ports-1 downto 0);
+  signal cnx_master_out : t_wishbone_master_out_array(c_cnx_master_ports-1 downto 0);
+
+  signal periph_out : t_wishbone_master_out_array(0 to c_peripherals-1);
+  signal periph_in  : t_wishbone_master_in_array(0 to c_peripherals-1);
+
+
+  constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
+    (0 => x"00000000",                  -- CPU I-mem
+     1 => x"10000000",                  -- CPU D-mem
+     2 => x"20000000");                 -- Peripherals
+
+  constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
+    (0 => x"f0000000",
+     1 => x"f0000000",
+     2 => x"f0000000");
+
+  signal owr_en_slv, owr_in_slv : std_logic_vector(0 downto 0);
+  
+begin  -- rtl
+
+  U_CPU : xwb_lm32
+    generic map (
+      g_profile => "medium")
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      irq_i     => x"00000000",
+      dwb_o     => cnx_slave_in(0),
+      dwb_i     => cnx_slave_out(0),
+      iwb_o     => cnx_slave_in(1),
+      iwb_i     => cnx_slave_out(1));
+
+  U_Intercon : xwb_crossbar
+    generic map (
+      g_num_masters => c_cnx_slave_ports,
+      g_num_slaves  => c_cnx_master_ports,
+      g_registered  => false)
+    port map (
+      clk_sys_i     => clk_sys_i,
+      rst_n_i       => rst_n_i,
+      slave_i       => cnx_slave_in,
+      slave_o       => cnx_slave_out,
+      master_i      => cnx_master_in,
+      master_o      => cnx_master_out,
+      cfg_address_i => c_cfg_base_addr,
+      cfg_mask_i    => c_cfg_base_mask);
+
+  U_DPRAM : xwb_dpram
+    generic map (
+      g_size                  => 8192,
+      g_init_file             => "sw/main.ram",
+      g_must_have_init_file   => true,
+      g_slave1_interface_mode => PIPELINED,
+      g_slave2_interface_mode => PIPELINED,
+      g_slave1_granularity    => BYTE,
+      g_slave2_granularity    => BYTE)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave1_i  => cnx_master_out(0),
+      slave1_o  => cnx_master_in(0),
+      slave2_i  => cnx_master_out(1),
+      slave2_o  => cnx_master_in(1));
+
+  U_peripheral_Fanout : xwb_bus_fanout
+    generic map (
+      g_num_outputs          => c_peripherals,
+      g_bits_per_slave       => 8,
+      g_address_granularity  => BYTE,
+      g_slave_interface_mode => PIPELINED)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => cnx_master_out(2),
+      slave_o   => cnx_master_in(2),
+      master_i  => periph_in,
+      master_o  => periph_out);
+
+  U_GPIO : xwb_gpio_port
+    generic map (
+      g_interface_mode         => CLASSIC,
+      g_address_granularity    => BYTE,
+      g_num_pins               => 32,
+      g_with_builtin_tristates => true)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => periph_out(0),
+      slave_o   => periph_in(0),
+      gpio_b    => gpio_b,
+      gpio_in_i => x"00000000"
+      );
+
+  U_UART : xwb_simple_uart
+    generic map (
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      slave_i    => periph_out(1),
+      slave_o    => periph_in(1),
+      uart_rxd_i => rxd_i,
+      uart_txd_o => txd_o);
+
+  U_OneWire : xwb_onewire_master
+    generic map (
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE,
+      g_num_ports           => 1)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => periph_out(2),
+      slave_o   => periph_in(2),
+      owr_en_o  => owr_en_slv,
+      owr_i     => owr_in_slv);
+
+  onewire_b <= '0' when owr_en_slv(0) = '1' else 'Z';
+  owr_in_slv(0) <= onewire_b;
+end rtl;

testbench/wishbone/lm32_testsys/main.sv

+`timescale 1ns/1ps
+
+module main;
+
+   reg clk_sys  =0;
+   reg rst_n    = 0;
+
+   always #5 clk_sys <= ~clk_sys;
+   
+   initial begin
+      repeat(3) @(posedge clk_sys);
+      rst_n  = 1;
+   end
+
+   
+   lm32_test_system
+     DUT (
+          .clk_sys_i (clk_sys),
+          .rst_n_i   (rst_n),
+          .gpio_b ()
+          );
+   
+                            
+
+endmodule // main
+
+

testbench/wishbone/lm32_testsys/manifest.py

+action = "simulation"
+target = "simulation"
+
+modules = {"local" : [ "../../.." ]	};
+files = ["main.sv", "lm32_test_system.vhd"]		

testbench/wishbone/lm32_testsys/run.do

+make
+
+vsim -L XilinxCoreLib -L secureip work.main -voptargs="+acc"
+radix -hexadecimal
+do wave.do
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+run 100us
+wave zoomfull
\ No newline at end of file

testbench/wishbone/lm32_testsys/sw/main.ram

+write 0 98000000
+write 1 D0000000
+write 2 D0200000
+write 3 78010000
+write 4 38210000
+write 5 D0E10000
+write 6 F800003A
+write 7 34000000
+write 8 00000000
+write 9 00000000
+write a 00000000
+write b 00000000
+write c 00000000
+write d 00000000
+write e 00000000
+write f 00000000
+write 10 00000000
+write 11 00000000
+write 12 00000000
+write 13 00000000
+write 14 00000000
+write 15 00000000
+write 16 00000000
+write 17 00000000
+write 18 00000000
+write 19 00000000
+write 1a 00000000
+write 1b 00000000
+write 1c 00000000
+write 1d 00000000
+write 1e 00000000
+write 1f 00000000
+write 20 00000000
+write 21 00000000
+write 22 00000000
+write 23 00000000
+write 24 00000000
+write 25 00000000
+write 26 00000000
+write 27 00000000
+write 28 00000000
+write 29 00000000
+write 2a 00000000
+write 2b 00000000
+write 2c 00000000
+write 2d 00000000
+write 2e 00000000
+write 2f 00000000
+write 30 5B9D0000
+write 31 F8000020
+write 32 34010002
+write 33 F8000041
+write 34 E0000030
+write 35 34000000
+write 36 34000000
+write 37 34000000
+write 38 00000000
+write 39 00000000
+write 3a 00000000
+write 3b 00000000
+write 3c 00000000
+write 3d 00000000
+write 3e 00000000
+write 3f 00000000
+write 40 98000000
+write 41 781C0000
+write 42 3B9CFFFC
+write 43 781A0000
+write 44 3B5A8390
+write 45 78010000
+write 46 38210394
+write 47 34020000
+write 48 78030000
+write 49 38630394
+write 4a C8611800
+write 4b F800005F
+write 4c 34010000
+write 4d 34020000
+write 4e 34030000
+write 4f F8000026
+write 50 E0000000
+write 51 379CFFC4
+write 52 5B810004
+write 53 5B820008
+write 54 5B83000C
+write 55 5B840010
+write 56 5B850014
+write 57 5B860018
+write 58 5B87001C
+write 59 5B880020
+write 5a 5B890024
+write 5b 5B8A0028
+write 5c 5B9E0034
+write 5d 5B9F0038
+write 5e 2B81003C
+write 5f 5B810030
+write 60 BB800800
+write 61 3421003C
+write 62 5B81002C
+write 63 C3A00000
+write 64 2B810004
+write 65 2B820008
+write 66 2B83000C
+write 67 2B840010
+write 68 2B850014
+write 69 2B860018
+write 6a 2B87001C
+write 6b 2B880020
+write 6c 2B890024
+write 6d 2B8A0028
+write 6e 2B9D0030
+write 6f 2B9E0034
+write 70 2B9F0038
+write 71 2B9C002C
+write 72 34000000
+write 73 C3C00000
+write 74 C3A00000
+write 75 379CFFFC
+write 76 5B9D0004
+write 77 F8000014
+write 78 34010055
+write 79 F8000017
+write 7a 34010055
+write 7b F8000015
+write 7c 34010055
+write 7d F8000013
+write 7e 34010055
+write 7f F8000011
+write 80 34010055
+write 81 F800000F
+write 82 34010055
+write 83 F800000D
+write 84 34010055
+write 85 F800000B
+write 86 34010055
+write 87 F8000009
+write 88 2B9D0004
+write 89 379C0004
+write 8a C3A00000
+write 8b 78012000
+write 8c 38210100
+write 8d 3402147B
+write 8e 58220004
+write 8f C3A00000
+write 90 379CFFFC
+write 91 5B9D0004
+write 92 78022000
+write 93 202300FF
+write 94 38420100
+write 95 28410000
+write 96 20210001
+write 97 5C20FFFE
+write 98 58430008
+write 99 3401000A
+write 9a 5C610003
+write 9b 3401000D
+write 9c FBFFFFF4
+write 9d 2B9D0004
+write 9e 379C0004
+write 9f C3A00000
+write a0 78012000
+write a1 38210100
+write a2 28210000
+write a3 20210002
+write a4 C3A00000
+write a5 78012000
+write a6 38210100
+write a7 2821000C
+write a8 202100FF
+write a9 C3A00000
+write aa B8204000
+write ab B8202800
+write ac 34010003
+write ad B8602000
+write ae 204900FF
+write af 50230023
+write b0 A1010800
+write b1 44200009
+write b2 212200FF
+write b3 34030000
+write b4 B4A30800
+write b5 30220000
+write b6 34630001
+write b7 5C64FFFD
+write b8 B9000800
+write b9 C3A00000
+write ba 3D210008
+write bb 3403000F
+write bc B8290800
+write bd 3C220010
+write be B9003800
+write bf B8412800
+write c0 B8603000
+write c1 B9000800
+write c2 B8801000
+write c3 54830011
+write c4 34030000
+write c5 34060003
+write c6 B4E31000
+write c7 34630004
+write c8 58450000
+write c9 C8830800
+write ca 5426FFFC
+write cb 3482FFFC
+write cc 00410002
+write cd 20440003
+write ce 34210001
+write cf 3C210002
+write d0 B4E13800
+write d1 B8E02800
+write d2 5C80FFE0
+write d3 E3FFFFE5
+write d4 58250000
+write d5 58250004
+write d6 58250008
+write d7 5825000C
+write d8 3442FFF0
+write d9 34210010
+write da 5446FFFA
+write db 3481FFF0
+write dc 00220004
+write dd 2024000F
+write de 34420001
+write df 3C420004
+write e0 34010003
+write e1 B5023800
+write e2 5481FFE2
+write e3 B8E02800
+write e4 E3FFFFEE
+write e5 E3FFFFEE

testbench/wishbone/lm32_testsys/wave.do

+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/g_with_virtual_uart
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/g_with_physical_uart
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/g_interface_mode
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/g_address_granularity
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/clk_sys_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/rst_n_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_adr_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_dat_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_dat_o
+add wave -noupdate /main/DUT/U_CPU/dwb_o
+add wave -noupdate /main/DUT/U_CPU/dwb_i
+add wave -noupdate /main/DUT/U_CPU/iwb_o
+add wave -noupdate /main/DUT/U_CPU/iwb_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_cyc_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_sel_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_stb_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_we_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_ack_o
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_stall_o
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/uart_rxd_i
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/uart_txd_o
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/rx_ready_reg
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/rx_ready
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/uart_bcr
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/rdr_rack
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/host_rack
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/baud_tick
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/baud_tick8
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/resized_addr
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_in
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/wb_out
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/regs_in
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/regs_out
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/fifo_empty
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/fifo_full
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/fifo_rd
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/fifo_wr
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/fifo_count
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/phys_rx_ready
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/phys_tx_busy
+add wave -noupdate /main/DUT/U_UART/U_Wrapped_UART/phys_rx_data
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {5032567 ps} 0}
+configure wave -namecolwidth 350
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {1751287 ps} {8313847 ps}