# Please enter a commit message to explain why this merge is necessary,
# especially if it merges an updated upstream into a topic branch.
#
# Lines starting with '#' will be ignored, and an empty message aborts
# the commit.

- the clock should be clk_sys_62m5
- DDR controller in the SPEC assumes WORD addressing on Wishbone

testbench/include: fix TDC EIC register addresses. THEY ARE BADLY GENERATED by WBGEN, if the driver uses a wbgen-produced .h file cross-check agains the .vh file in this commit!

- initialize TDC DMA Engine (buffer controller)
- reset the SPEC/DDR contoller prior to operation (still wip)
- feed the design with fake timestamps bypassing ACAM, let's debug one thing at a time.

This is a WIP commit, I see the core writing the timestamps to the DDR, but the Gennum-side DMA as well as double-buffering of the DDR timestamps is yet to be implemented.

Note: I've never managed to simulate DMA with the crappy Gennum VHDL model. I guess we need to fix it or write a new one..

wr_spec_tdc: expose sim_timestamp interface to feed fake timestamps to the core without modelling the ACAM chip

- code cleanup: removal of unused signals and of the unused tstamps subtractions

This reduces the required resources since we only use one set of adders for all channels (instead of one per).

There is no issue with multiple timestamps arriving simultaneously, since the previous stages serialise the
delivery of timestamps and this stage is fully pipelined, so it can process one timestamp per cycle.

[hdl] do not filter out falling edges in direct readout. This can be done if necessary by setting the relevant ACAM registers

Previous fix did not correctly account for when the most significant bit of a.frac was '1', as it would incorrectly consider it as a negative number.

Also updated the header notes.