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FMC TDC 1ns 5cha
Commits
ac0bebbb
Commit
ac0bebbb
authored
Apr 22, 2020
by
Evangelia Gousiou
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cosmetics
parent
a34d839c
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4 changed files
with
72 additions
and
71 deletions
+72
-71
fmc_tdc_core.vhd
hdl/rtl/fmc_tdc_core.vhd
+27
-28
fmc_tdc_mezzanine.vhd
hdl/rtl/fmc_tdc_mezzanine.vhd
+31
-31
wr_spec_tdc.xise
hdl/syn/spec/wr_spec_tdc.xise
+2
-2
wr_spec_tdc.vhd
hdl/top/spec/wr_spec_tdc.vhd
+12
-10
No files found.
hdl/rtl/fmc_tdc_core.vhd
View file @
ac0bebbb
...
...
@@ -123,19 +123,19 @@ use work.genram_pkg.all;
--=================================================================================================
entity
fmc_tdc_core
is
generic
(
g_
span
:
integer
:
=
32
;
-- address span in bus interfaces
g_
width
:
integer
:
=
32
;
-- data width in bus interfaces
g_
simulation
:
boolean
:
=
false
;
(
g_
SPAN
:
integer
:
=
32
;
-- address span in bus interfaces
g_
WIDTH
:
integer
:
=
32
;
-- data width in bus interfaces
g_
SIMULATION
:
boolean
:
=
FALSE
;
-- Enable filtering based on pulse width. This will have the following effects:
-- * Suppress theforwarding of negative slope timestamps.
-- * Delay the forwarding of timestamps until after the falling edge timestamp.
-- Once enabled, all pulses wider than 1 second or narrower than
-- g_pulse_width_filter_min will be dropped.
g_
pulse_width_filter
:
boolean
:
=
true
;
g_
PULSE_WIDTH_FILTER
:
boolean
:
=
true
;
-- In 8ns ticks.
g_
pulse_width_filter_min
:
natural
:
=
12
;
g_
with_dma_readout
:
boolean
:
=
false
;
g_
with_fifo_readout
:
boolean
:
=
false
);
g_
PULSE_WIDTH_FILTER_MIN
:
natural
:
=
12
;
g_
USE_DMA_READOUT
:
boolean
:
=
FALSE
;
g_
USE_FIFO_READOUT
:
boolean
:
=
FALSE
);
port
(
clk_sys_i
:
in
std_logic
;
...
...
@@ -174,8 +174,8 @@ entity fmc_tdc_core is
tdc_led_trig_o
:
out
std_logic_vector
(
4
downto
0
);
-- one amber led on front pannel per Ch
-- White Rabbit control and status registers
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_
width
-1
downto
0
);
wrabbit_ctrl_reg_o
:
out
std_logic_vector
(
g_
width
-1
downto
0
);
wrabbit_status_reg_i
:
in
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
wrabbit_ctrl_reg_o
:
out
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
-- White Rabbit timing
wrabbit_synched_i
:
in
std_logic
;
wrabbit_tai_p_i
:
in
std_logic
;
...
...
@@ -212,10 +212,10 @@ architecture rtl of fmc_tdc_core is
-- ACAM communication
signal
acm_adr
:
std_logic_vector
(
7
downto
0
);
signal
acm_cyc
,
acm_stb
,
acm_we
,
acm_ack
:
std_logic
;
signal
acm_dat_r
,
acm_dat_w
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
acm_dat_r
,
acm_dat_w
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
signal
acam_ef1
,
acam_ef2
:
std_logic
;
signal
acam_intflag_f_edge_p
:
std_logic
;
signal
acam_tstamp1
,
acam_tstamp2
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
acam_tstamp1
,
acam_tstamp2
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
signal
acam_tstamp1_ok_p
,
acam_tstamp2_ok_p
:
std_logic
;
-- control unit
signal
activate_acq_p
,
deactivate_acq_p
,
load_acam_config
:
std_logic
;
...
...
@@ -223,20 +223,20 @@ architecture rtl of fmc_tdc_core is
signal
read_ififo2
,
read_start01
,
reset_acam
,
load_utc
:
std_logic
;
signal
roll_over_incr_recent
:
std_logic
;
signal
deactivate_chan
:
std_logic_vector
(
4
downto
0
);
signal
clk_period
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
starting_utc
,
acam_inputs_en
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
acam_ififo1
,
acam_ififo2
,
acam_start01
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
irq_tstamp_threshold
,
irq_time_threshold
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
local_utc
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
clk_period
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
signal
starting_utc
,
acam_inputs_en
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
signal
acam_ififo1
,
acam_ififo2
,
acam_start01
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
signal
irq_tstamp_threshold
,
irq_time_threshold
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
signal
local_utc
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
signal
acam_config
,
acam_config_rdbk
:
config_vector
;
signal
start_from_fpga
,
state_active_p
:
std_logic
;
-- retrigger control
signal
clk_i_cycles_offset
,
roll_over_nb
,
retrig_nb_offset
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
clk_i_cycles_offset
,
roll_over_nb
,
retrig_nb_offset
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
signal
local_utc_p
:
std_logic
;
signal
current_retrig_nb
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
current_retrig_nb
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
-- UTC
signal
utc_p
:
std_logic
;
signal
utc
,
wrabbit_ctrl_reg
:
std_logic_vector
(
g_
width
-1
downto
0
);
signal
utc
,
wrabbit_ctrl_reg
:
std_logic_vector
(
g_
WIDTH
-1
downto
0
);
-- LEDs
signal
term_enable_tdc
:
std_logic_vector
(
4
downto
0
);
...
...
@@ -272,15 +272,15 @@ begin
-- TDC REGISTERS CONTROLLER --
---------------------------------------------------------------------------------------------------
core_status
(
0
)
<=
'1'
when
g_
with_dma_readout
else
'0'
;
core_status
(
1
)
<=
'1'
when
g_
with_fifo_readout
else
'0'
;
core_status
(
0
)
<=
'1'
when
g_
USE_DMA_READOUT
else
'0'
;
core_status
(
1
)
<=
'1'
when
g_
USE_FIFO_READOUT
else
'0'
;
core_status
(
2
)
<=
fmc_id_i
;
core_status
(
31
downto
3
)
<=
(
others
=>
'0'
);
reg_control_block
:
entity
work
.
reg_ctrl
generic
map
(
g_span
=>
g_span
,
g_
width
=>
g_width
)
g_
WIDTH
=>
g_WIDTH
)
port
map
(
clk_tdc_i
=>
clk_tdc_i
,
rst_tdc_n_i
=>
rst_tdc_n_i
,
...
...
@@ -365,7 +365,7 @@ begin
---------------------------------------------------------------------------------------------------
local_one_second_block
:
entity
work
.
local_pps_gen
generic
map
(
g_
width
=>
g_width
)
(
g_
WIDTH
=>
g_WIDTH
)
port
map
(
acam_refclk_r_edge_p_i
=>
acam_refclk_r_edge_p_i
,
clk_i
=>
clk_tdc_i
,
...
...
@@ -510,12 +510,11 @@ begin
-- TSTAMP FINAL FORMAT --
-- ADDITION OF FIXED OFFSETS (PER CHANNEL CALIBRATION) --
-- FILTERING BY PULSE WIDTH --
-- SUBTRACTIONS BETWEEN CHANNELS --
---------------------------------------------------------------------------------------------------
U_FilterAndConvert
:
entity
work
.
timestamp_convert_filter
generic
map
(
g_pulse_width_filter
=>
g_
pulse_width_filter
,
g_pulse_width_filter_min
=>
g_
pulse_width_filter_min
)
g_pulse_width_filter
=>
g_
PULSE_WIDTH_FILTER
,
g_pulse_width_filter_min
=>
g_
PULSE_WIDTH_FILTER_MIN
)
port
map
(
clk_tdc_i
=>
clk_tdc_i
,
rst_tdc_n_i
=>
rst_tdc_n_i
,
...
...
@@ -549,7 +548,7 @@ begin
---------------------------------------------------------------------------------------------------
TDCboard_leds
:
entity
work
.
leds_manager
generic
map
(
g_
width
=>
32
,
(
g_
WIDTH
=>
32
,
g_simulation
=>
g_simulation
)
port
map
(
clk_i
=>
clk_tdc_i
,
...
...
@@ -567,7 +566,7 @@ begin
U_Sync_ChannelEnable
:
entity
work
.
gc_sync_register
generic
map
(
g_
width
=>
5
)
g_
WIDTH
=>
5
)
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_a_i
=>
rst_sys_n_i
,
...
...
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @
ac0bebbb
...
...
@@ -92,21 +92,21 @@ use work.TDC_OW_wbgen2_pkg.all;
--=================================================================================================
entity
fmc_tdc_mezzanine
is
generic
(
g_
with_wrabbit_core
:
boolean
:
=
true
;
g_
span
:
integer
:
=
32
;
g_
width
:
integer
:
=
32
;
g_
simulation
:
boolean
:
=
false
;
(
g_
WITH_WRABBIT_CORE
:
boolean
:
=
TRUE
;
g_
SPAN
:
integer
:
=
32
;
g_
WIDTH
:
integer
:
=
32
;
g_
SIMULATION
:
boolean
:
=
FALSE
;
-- Enable filtering based on pulse width. This will have the following effects:
-- * Suppress theforwarding of negative slope timestamps.
-- * Delay the forwarding of timestamps until after the falling edge timestamp.
-- Once enabled, all pulses wider than 1 second or narrower than
-- g_
pulse_width_filter_min
will be dropped.
g_
pulse_width_filter
:
boolean
:
=
true
;
-- g_
PULSE_WIDTH_FILTER_MIN
will be dropped.
g_
PULSE_WIDTH_FILTER
:
boolean
:
=
TRUE
;
-- In 8ns ticks.
g_
pulse_width_filter_min
:
natural
:
=
12
;
g_
use_dma_readout
:
boolean
:
=
true
;
g_
use_fifo_readout
:
boolean
:
=
true
;
g_
use_fake_timestamps_for_sim
:
boolean
:
=
false
);
g_
PULSE_WIDTH_FILTER_MIN
:
natural
:
=
12
;
g_
USE_DMA_READOUT
:
boolean
:
=
TRUE
;
g_
USE_FIFO_READOUT
:
boolean
:
=
TRUE
;
g_
USE_FAKE_TIMESTAMPS_FOR_SIM
:
boolean
:
=
FALSE
);
port
-- TDC core
(
...
...
@@ -303,8 +303,8 @@ begin
generic
map
(
g_num_masters
=>
c_NUM_WB_SLAVES
,
g_num_slaves
=>
c_NUM_WB_MASTERS
,
g_registered
=>
true
,
g_wraparound
=>
true
,
g_registered
=>
TRUE
,
g_wraparound
=>
TRUE
,
g_layout
=>
c_INTERCONNECT_LAYOUT
,
g_sdb_addr
=>
c_SDB_ADDRESS
)
port
map
...
...
@@ -321,13 +321,13 @@ begin
---------------------------------------------------------------------------------------------------
cmp_tdc_core
:
entity
work
.
fmc_tdc_core
generic
map
(
g_
span
=>
g_span
,
g_
width
=>
g_width
,
g_
simulation
=>
g_simulation
,
g_
pulse_width_filter
=>
g_pulse_width_filter
,
g_
pulse_width_filter_min
=>
g_pulse_width_filter_min
,
g_
with_dma_readout
=>
g_use_dma_readout
,
g_
with_fifo_readout
=>
g_use_fifo_readout
)
(
g_
SPAN
=>
g_SPAN
,
g_
WIDTH
=>
g_WIDTH
,
g_
SIMULATION
=>
g_SIMULATION
,
g_
PULSE_WIDTH_FILTER
=>
g_PULSE_WIDTH_FILTER
,
g_
PULSE_WIDTH_FILTER_MIN
=>
g_PULSE_WIDTH_FILTER_MIN
,
g_
USE_DMA_READOUT
=>
g_USE_DMA_READOUT
,
g_
USE_FIFO_READOUT
=>
g_USE_FIFO_READOUT
)
port
map
(
-- clks, rst
clk_tdc_i
=>
clk_tdc_i
,
...
...
@@ -398,7 +398,7 @@ begin
gen_fifos
:
for
i
in
0
to
4
generate
U_TheFifo
:
entity
work
.
timestamp_fifo
generic
map
(
g_
use_fifo_readout
=>
g_use_fifo_readout
)
g_
USE_FIFO_READOUT
=>
g_USE_FIFO_READOUT
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_sys_n_i
=>
rst_sys_n_i
,
...
...
@@ -421,7 +421,7 @@ begin
---------------------------------------------------------------------------------------------------
-- DMA --
---------------------------------------------------------------------------------------------------
gen_with_dma_readout
:
if
g_
use_dma_readout
generate
gen_with_dma_readout
:
if
g_
USE_DMA_READOUT
generate
U_DMA_Engine
:
entity
work
.
tdc_dma_engine
generic
map
(
g_CLOCK_FREQ
=>
62500000
)
...
...
@@ -441,7 +441,7 @@ begin
end
generate
gen_with_dma_readout
;
gen_without_dma
:
if
not
g_
use_dma_readout
generate
gen_without_dma
:
if
not
g_
USE_DMA_READOUT
generate
irq_dma
<=
(
others
=>
'0'
);
cnx_master_in
(
c_WB_SLAVE_TDC_DMA
)
.
stall
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_TDC_DMA
)
.
err
<=
'0'
;
...
...
@@ -470,12 +470,12 @@ begin
end
process
;
---------------------------------------------------------------------------------------------------
-- WHITE RABBIT STUFF --
-- only synthesized if g_
with_wrabbit_core
is TRUE --
-- only synthesized if g_
WITH_WRABBIT_CORE
is TRUE --
---------------------------------------------------------------------------------------------------
cmp_wrabbit_synch
:
wrabbit_sync
generic
map
(
g_
simulation
=>
g_simulation
,
g_
with_wrabbit_core
=>
g_with_wrabbit_core
)
(
g_
SIMULATION
=>
g_SIMULATION
,
g_
WITH_WRABBIT_CORE
=>
g_WITH_WRABBIT_CORE
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_sys_i
=>
rst_sys_n_i
,
...
...
@@ -499,7 +499,7 @@ begin
if
rst_tdc_n_i
=
'0'
then
wrabbit_utc_p
<=
'0'
;
else
if
wrabbit_clk_aux_locked_i
=
'1'
and
g_
with_wrabbit_core
then
if
wrabbit_clk_aux_locked_i
=
'1'
and
g_
WITH_WRABBIT_CORE
then
-- so that the end of the pulse comes exactly upon the UTC change
if
unsigned
(
wrabbit_cycles_i
)
=
(
unsigned
(
c_CLK_PERIOD
)
-
3
)
then
wrabbit_utc_p
<=
'1'
;
...
...
@@ -521,7 +521,7 @@ begin
U_OnewireIF
:
gc_ds182x_readout
generic
map
(
g_CLOCK_FREQ_KHZ
=>
62500
,
g_USE_INTERNAL_PPS
=>
true
)
g_USE_INTERNAL_PPS
=>
TRUE
)
port
map
(
clk_i
=>
clk_sys_i
,
rst_n_i
=>
rst_sys_n_i
,
...
...
@@ -551,7 +551,7 @@ begin
-- 1 -> number of seconds passed reached threshold and number of accumulated tstamps > 0
-- 2 -> ACAM error
gen_enable_eic
:
if
g_
use_fifo_readout
or
g_use_dma_readout
generate
gen_enable_eic
:
if
g_
USE_FIFO_READOUT
or
g_USE_DMA_READOUT
generate
cmp_tdc_eic
:
entity
work
.
tdc_eic
port
map
(
clk_sys_i
=>
clk_sys_i
,
...
...
@@ -579,7 +579,7 @@ begin
);
end
generate
gen_enable_eic
;
gen_disable_eic
:
if
not
g_
use_fifo_readout
and
not
g_use_dma_readout
generate
gen_disable_eic
:
if
not
g_
USE_FIFO_READOUT
and
not
g_USE_DMA_READOUT
generate
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
ack
<=
'1'
;
cnx_master_in
(
c_WB_SLAVE_TDC_EIC
)
.
stall
<=
'0'
;
wb_irq_o
<=
'0'
;
...
...
@@ -617,7 +617,7 @@ begin
i2c_scl_oen_o
<=
sys_scl_oe_n
;
i2c_scl_o
<=
sys_scl_out
;
gen_use_fake_timestamps
:
if
g_
use_fake_timestamps_for_sim
generate
gen_use_fake_timestamps
:
if
g_
USE_FAKE_TIMESTAMPS_FOR_SIM
generate
process
(
sim_timestamp_i
,
sim_timestamp_valid_i
)
begin
...
...
@@ -636,7 +636,7 @@ begin
end
generate
gen_use_fake_timestamps
;
gen_use_real_timestamps
:
if
not
g_
use_fake_timestamps_for_sim
generate
gen_use_real_timestamps
:
if
not
g_
USE_FAKE_TIMESTAMPS_FOR_SIM
generate
timestamp
<=
tdc_timestamp
;
timestamp_valid
<=
tdc_timestamp_valid
;
tdc_timestamp_ready
<=
timestamp_ready
;
...
...
hdl/syn/spec/wr_spec_tdc.xise
View file @
ac0bebbb
...
...
@@ -1323,7 +1323,7 @@
<property
xil_pn:name=
"Register Balancing"
xil_pn:value=
"Yes"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Register Duplication Map"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Duplication Xst"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Ordering spartan6"
xil_pn:value=
"
4"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Register Ordering spartan6"
xil_pn:value=
"
8"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Release Set/Reset (Output Events)"
xil_pn:value=
"Default (6)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Release Write Enable (Output Events)"
xil_pn:value=
"Default (6)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Design Instance in Testbench File to"
xil_pn:value=
"UUT"
xil_pn:valueState=
"default"
/>
...
...
@@ -1394,7 +1394,7 @@
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Translate"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Speed Grade"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Starting Placer Cost Table (1-100) Map"
xil_pn:value=
"1"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Starting Placer Cost Table (1-100) Map spartan6"
xil_pn:value=
"
3
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Starting Placer Cost Table (1-100) Map spartan6"
xil_pn:value=
"
42
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Starting Placer Cost Table (1-100) Par"
xil_pn:value=
"1"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Structure window"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Symbolic FSM Compiler"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
...
...
hdl/top/spec/wr_spec_tdc.vhd
View file @
ac0bebbb
...
...
@@ -102,10 +102,12 @@ use UNISIM.vcomponents.all;
entity
wr_spec_tdc
is
generic
(
g_WRPC_INITF
:
string
:
=
"../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram"
;
g_simulation
:
boolean
:
=
false
;
g_use_dma_readout
:
boolean
:
=
true
;
g_use_fake_timestamps_for_sim
:
boolean
:
=
false
-- when instantiated in a test-bench
(
g_WRPC_INITF
:
string
:
=
"../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram"
;
g_WITH_DIRECT_READOUT
:
boolean
:
=
FALSE
;
-- for embedded applications, like WRTD
g_USE_FIFO_READOUT
:
boolean
:
=
TRUE
;
-- 1x 64-tstamps-long FIFO per channel; used on SVEC
g_USE_DMA_READOUT
:
boolean
:
=
TRUE
;
-- DMA; used on SPEC
g_SIMULATION
:
boolean
:
=
FALSE
;
-- TRUE only in sim
g_USE_FAKE_TIMESTAMPS_FOR_SIM
:
boolean
:
=
FALSE
-- when instantiated in a test-bench
);
port
(
...
...
@@ -634,11 +636,11 @@ begin
cmp_fmc_tdc_mezzanine
:
entity
work
.
fmc_tdc_wrapper
generic
map
(
g_
simulation
=>
g_simulation
,
g_
with_direct_readout
=>
false
,
-- for embedded applications, like WRTD
g_
use_dma_readout
=>
g_use_dma_readout
,
g_
use_fifo_readout
=>
TRUE
,
g_
use_fake_timestamps_for_sim
=>
g_use_fake_timestamps_for_sim
)
g_
WITH_DIRECT_READOUT
=>
g_WITH_DIRECT_READOUT
,
g_
USE_DMA_READOUT
=>
g_USE_DMA_READOUT
,
g_
USE_FIFO_READOUT
=>
g_USE_FIFO_READOUT
,
g_
SIMULATION
=>
g_SIMULATION
,
g_
USE_FAKE_TIMESTAMPS_FOR_SIM
=>
g_USE_FAKE_TIMESTAMPS_FOR_SIM
)
port
map
(
clk_sys_i
=>
clk_sys_62m5
,
rst_sys_n_i
=>
rst_sys_62m5_n
,
...
...
@@ -721,7 +723,7 @@ begin
cmp_pci_access_led
:
gc_extend_pulse
generic
map
(
g_
width
=>
2500000
)
g_
WIDTH
=>
2500000
)
port
map
(
clk_i
=>
clk_sys_62m5
,
rst_n_i
=>
rst_sys_62m5_n
,
...
...
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