Commit d4939966 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/tdc_dma_engine: use faster IRQ timeout tick period when running in simulation mode

parent b5bce5a8
......@@ -448,7 +448,8 @@ begin
gen_with_dma_readout : if g_USE_DMA_READOUT generate
U_DMA_Engine : entity work.tdc_dma_engine
generic map (
g_CLOCK_FREQ => 62500000)
g_CLOCK_FREQ => 62500000,
g_SIMULATION => g_SIMULATION)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
......
......@@ -10,7 +10,8 @@ use work.gencores_pkg.all;
entity tdc_dma_engine is
generic (
g_CLOCK_FREQ : integer := 62500000
g_CLOCK_FREQ : integer := 62500000;
g_SIMULATION : boolean := false
);
port (
clk_i : in std_logic;
......@@ -55,9 +56,19 @@ architecture rtl of tdc_dma_engine is
3 => x"000001c0",
4 => x"000001c0");
constant c_TIMER_PERIOD_MS : integer := 1;
constant c_TIMER_DIVIDER_VALUE : integer := g_CLOCK_FREQ * c_TIMER_PERIOD_MS / 1000 - 1;
impure function f_pick_timer_divider return integer is
begin
if g_SIMULATION then
return 1000;
else
return g_CLOCK_FREQ * c_TIMER_PERIOD_MS / 1000 - 1;
end if;
end f_pick_timer_divider;
constant c_TIMER_DIVIDER_VALUE : integer := f_pick_timer_divider;
signal irq_tick_div : unsigned(15 downto 0);
signal irq_tick : std_logic;
......
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