Skip to content

F
FMC TDC 1ns 5cha
Commit 575ea362 authored by Evangelia Gousiou's avatar Evangelia Gousiou
Browse files
Options

wip cleanup of file headers

parent 181fbd42
Hide whitespace changes
Inline Side-by-side
Showing with 11 additions and 161 deletions
hdl/rtl/acam_databus_interface.vhd
View file @ 575ea362
......@@ -38,20 +38,6 @@
-- defines that the maximum ef set time is 11.8 ns; this allows for >4 ns for the signals routing.|
-- To make sure this constraint is met, the Xilinx design map option "Pack IO Registers/Lathes |
-- into IOBs" should be enabled. |
--------------------------------------------------------------------------------------------------|
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 08/2013 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 10/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 08/2013 v1. EG cs_n_o always active |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......
hdl/rtl/acam_timecontrol_interface.vhd
View file @ 575ea362
......@@ -12,24 +12,10 @@
---------------------------------------------------------------------------------------------------
-- File acam_timecontrol_interface.vhd |
-- |
-- Description interface with the ACAM chip pins for control and timing. |
-- Description Interface with the ACAM chip pins for control and timing. |
-- the start pulse is sent only once upon the activation of the acquisition, |
-- synchronously to the utc_p_i |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 04/2014 v2 EG Changed the generation of the start_from_fpga; synchronous to utc_p and |
-- after the signalling from the data_engine that state_active_p_i |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......
hdl/rtl/clks_rsts_manager.vhd
View file @ 575ea362
......@@ -17,7 +17,7 @@
-- |
-- The PLL is programmed to generate a 125 MHz clock that arrives to the FPGA and |
-- is used by all the other units of the TDC core. |
-- It is also programmed to generates a 31.25 MHz clock which is the reference clock |
-- It is also programmed to generate a 31.25 MHz clock which is the reference clock |
-- for the ACAM chip. |
-- The registers for programming the PLL are hard-coded in this unit. |
-- |
......@@ -28,27 +28,10 @@
-- Note that the PLL needs to be configured on the falling edges of the sclk clock, |
-- whereas the DAC on the rising edges. |
-- |
-- The unit is also responsible for the generation of a global internal reset signal |
-- for the TDC core. This internal reset is triggered by a GN4124/VME interface |
-- reset or by a Power On Reset at startup. The idea is to keep this reset asserted |
-- until the 125 MHz clock signal received from the PLL is stable (PLL lock). |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 02/2014 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.2 EG Added DFFs to the pll_sdi_o, pll_cs_n_o outputs |
-- Changed completely the internal reset generation; now it depends |
-- on the pll_status activation |
-- General revamping, comments added, signals renamed |
-- 05/2012 v0.3 EG Added logic for DAC configuration |
-- 02/2014 v1 EG Correction for the DAC on rising edges; added wrabbit support |
-- The unit also generates of a global internal reset signal for the TDC core. |
-- This internal reset is triggered by a GN4124/VME interface reset or by a |
-- Power On Reset at startup and it remains asserted until the 125 MHz clock signal |
-- received from the PLL is stable (PLL lock). |
-- |
---------------------------------------------------------------------------------------------------
......
hdl/rtl/data_formatting.vhd
View file @ 575ea362
......@@ -18,26 +18,6 @@
-- o plus the coarse timing internally measured in the core |
-- o plus the UTC time, coming from the WRabbit core if synchronization is |
-- established or from the internal local counter |
-- and writes the word to the circular buffer |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2014 |
-- Version v3 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 04/2013 v1 EG Fixed bug when timestamp comes on the first retrigger after a new |
-- second; fixed bug on rollover that is a bit delayed wrt ACAM IrFlag |
-- 07/2013 v2 EG Cleaner writing with addition of intermediate DFF on the acam_tstamp |
-- calculations |
-- 09/2013 v2.1 EG added wr_index clearing upon dacapo_c_rst_p_i pulse; before only the |
-- dacapo_counter was being reset with the dacapo_c_rst_p_i |
-- 04/2014 v3 EG added logic for channels deactivation |
-- |
---------------------------------------------------------------------------------------------------
......@@ -86,7 +66,7 @@ entity data_formatting is
acam_tstamp2_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO2
-- Signals from the one_hz_gen unit
-- Signals from the one_hz_gen unit
utc_i : in std_logic_vector(31 downto 0); -- local UTC time
-- Signals from the start_retrig_ctrl unit
......
hdl/rtl/decr_counter.vhd
View file @ 575ea362
......@@ -17,18 +17,6 @@
-- "Counter done" signal asserted simultaneous to "current count value = 0". |
-- Countdown is launched each time "counter_load_i" is asserted for one clock tick. |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_core.vhd
View file @ 575ea362
......@@ -512,6 +512,7 @@ begin
-- TSTAMP FINAL FORMAT --
-- ADDITION OF OFFSETS (EX.CALIBRATION) --
-- FILTERING BY PULSE WIDTH --
-- SUBTRACTIONS BETWEEN CHANNELS --
---------------------------------------------------------------------------------------------------
U_FilterAndConvert : entity work.timestamp_convert_filter
generic map (
......@@ -531,9 +532,10 @@ begin
ts_ready_i => final_timestamp_ready,
ts_offset_i => ts_offset_i,
reset_seq_i => reset_seq_i,
raw_enable_i => raw_enable_i
raw_enable_i => raw_enable_i -- not used
);
---------------------------------------------------------------------------------------------------
-- UTC timing source --
---------------------------------------------------------------------------------------------------
......
hdl/rtl/free_counter.vhd
View file @ 575ea362
......@@ -16,18 +16,6 @@
-- "Current count value" and "counting done" signal available. |
-- "Counting done" signal asserted simultaneous to "current count value = 0". |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......
hdl/rtl/incr_counter.vhd
View file @ 575ea362
......@@ -17,18 +17,6 @@
-- "Counting done" signal asserted simultaneous to"current count value=counter_top_i"|
-- Needs a rst_i to restart. |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......
hdl/rtl/local_pps_gen.vhd
View file @ 575ea362
......@@ -18,18 +18,6 @@
-- If there is no White Rabbit synchronization, this unit is the source of UTC timing|
-- in the design.
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......
hdl/rtl/reg_ctrl.vhd
View file @ 575ea362
......@@ -31,19 +31,6 @@
-- |
-- All the registers are of size 32 bits, as the WISHBONE data bus |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 08/2012 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 10/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 08/2012 v1 EG added register reg_adr_pipe0 for slack timing reasons |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......
hdl/rtl/start_retrig_ctrl.vhd
View file @ 575ea362
......@@ -88,19 +88,6 @@
-- To conclude, the final Coarse time is: (Part(2) + Part(3)_Start#)*Retrigger period|
-- and the Fine time is : Part(3)_Hit |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2014 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 04/2014 v1 EG Changed roll_over_counter to add rare case where utc_p_i and |
-- acam_intflag_f_edge_p_i arrive at the same time |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -123,7 +110,7 @@
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific library
library work;
......
hdl/rtl/tdc_core_pkg.vhd
View file @ 575ea362
......@@ -14,19 +14,6 @@
-- |
-- Description Package containing core wide constants and components |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2011 v0.1 GP First version |
-- 04/2012 v0.2 EG Revamping; Gathering of all the constants, declarations of all the |
-- units; Comments added, signals renamed |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment