hdl/rtl/fine_delay_core.vhd: VCXO frequency measurement, FMC presence detection, new (generic-configured) WB Interconnect

hdl/rtl/fd_acam_timestamper.vhd: disable STOP input during processing of the pulse to avoid overloading the TDC FIFO when the stop input is driven with a very fast train of pulses

hdl: fd_delay_channel_driver.vhd: fixed RCR.CONT bit detection (now the core can produce continuous waveforms)