Commit c00e32c0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

hdl/rtl/fd_ring_buffer.vhd: fixed invalid DPRAM clock connection

parent 94dbf96b
......@@ -8,7 +8,5 @@ modelsim.ini
*.vstf
work
*.bak
syn/spec_1_1/*
syn/spec_wr_demo/*
syn/tests
syn/*
transcript
\ No newline at end of file
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2012-02-20
-- Last update: 2012-05-01
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -191,7 +191,7 @@ begin -- behavioral
g_dual_clock => false)
port map (
rst_n_i => rst_n_sys_i,
clka_i => clk_ref_i,
clka_i => clk_sys_i,
bwea_i => (others => '1'),
wea_i => buf_write,
aa_i => std_logic_vector(buf_wr_ptr),
......
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......@@ -3,4 +3,4 @@ action = "simulation"
vlog_opt="+incdir+../../include +incdir+../../include/wb"
files = "main.sv"
modules = {"local": [ "../../rtl" ] }
modules = {"local": [ "../../" ] }
This diff is collapsed.
make
#make
vsim -L XilinxCoreLib work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
do wave.do
run 1us
run 100us
wave zoomfull
\ No newline at end of file
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/clk_ref_i
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/trig_a_n_i
add wave -noupdate /main/DUT/trig_cal_o
add wave -noupdate /main/DUT/tdc_start_i
add wave -noupdate /main/DUT/led_trig_o
add wave -noupdate /main/DUT/acam_a_o
add wave -noupdate /main/DUT/acam_d_o
add wave -noupdate /main/DUT/acam_d_i
add wave -noupdate /main/DUT/acam_d_oen_o
add wave -noupdate /main/DUT/acam_err_i
add wave -noupdate /main/DUT/acam_int_i
add wave -noupdate /main/DUT/acam_emptyf_i
add wave -noupdate /main/DUT/acam_alutrigger_o
add wave -noupdate /main/DUT/acam_cs_n_o
add wave -noupdate /main/DUT/acam_wr_n_o
add wave -noupdate /main/DUT/acam_rd_n_o
add wave -noupdate /main/DUT/acam_start_dis_o
add wave -noupdate /main/DUT/acam_stop_dis_o
add wave -noupdate /main/DUT/spi_cs_dac_n_o
add wave -noupdate /main/DUT/spi_cs_pll_n_o
add wave -noupdate /main/DUT/spi_cs_gpio_n_o
add wave -noupdate /main/DUT/spi_sclk_o
add wave -noupdate /main/DUT/spi_mosi_o
add wave -noupdate /main/DUT/spi_miso_i
add wave -noupdate /main/DUT/delay_len_o
add wave -noupdate /main/DUT/delay_val_o
add wave -noupdate /main/DUT/delay_pulse_o
add wave -noupdate /main/DUT/wr_time_valid_i
add wave -noupdate /main/DUT/wr_coarse_i
add wave -noupdate /main/DUT/wr_utc_i
add wave -noupdate /main/DUT/owr_en_o
add wave -noupdate /main/DUT/owr_i
add wave -noupdate /main/DUT/wb_adr_i
add wave -noupdate /main/DUT/wb_dat_i
add wave -noupdate /main/DUT/wb_dat_o
add wave -noupdate /main/DUT/wb_cyc_i
add wave -noupdate /main/DUT/wb_stb_i
add wave -noupdate /main/DUT/wb_we_i
add wave -noupdate /main/DUT/wb_ack_o
add wave -noupdate /main/DUT/wb_irq_o
add wave -noupdate /main/DUT/tag_frac
add wave -noupdate /main/DUT/tag_coarse
add wave -noupdate /main/DUT/tag_utc
add wave -noupdate /main/DUT/tag_valid
add wave -noupdate /main/DUT/rbuf_frac
add wave -noupdate /main/DUT/rbuf_coarse
add wave -noupdate /main/DUT/rbuf_utc
add wave -noupdate /main/DUT/rbuf_valid
add wave -noupdate /main/DUT/master_csync_p1
add wave -noupdate /main/DUT/master_csync_utc
add wave -noupdate /main/DUT/master_csync_coarse
add wave -noupdate /main/DUT/rst_n_sys
add wave -noupdate /main/DUT/rst_n_ref
add wave -noupdate /main/DUT/advance_rbuf
add wave -noupdate /main/DUT/rbuf_irq
add wave -noupdate /main/DUT/tdc_rearm_p1
add wave -noupdate /main/DUT/tdc_start_p1
add wave -noupdate /main/DUT/dcr_enable_vec
add wave -noupdate /main/DUT/dcr_mode_vec
add wave -noupdate /main/DUT/chx_rearm
add wave -noupdate /main/DUT/chx_delay_pulse
add wave -noupdate /main/DUT/chx_delay_value
add wave -noupdate /main/DUT/chx_delay_load
add wave -noupdate /main/DUT/chx_delay_load_done
add wave -noupdate /main/DUT/fan_out
add wave -noupdate /main/DUT/fan_in
add wave -noupdate /main/DUT/wb_in
add wave -noupdate /main/DUT/wb_out
add wave -noupdate /main/DUT/regs_fromwb
add wave -noupdate /main/DUT/regs_towb_csync
add wave -noupdate /main/DUT/regs_towb_tsu
add wave -noupdate /main/DUT/regs_towb_rbuf
add wave -noupdate /main/DUT/regs_towb_local
add wave -noupdate /main/DUT/regs_towb
add wave -noupdate /main/DUT/spi_cs_vec
add wave -noupdate /main/DUT/owr_en_int
add wave -noupdate /main/DUT/owr_int
add wave -noupdate /main/DUT/dbg
add wave -noupdate /main/DUT/gen_cal_pulse
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_with_internal_timebase
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_clk_sys_freq
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/g_counter_bits
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/clk_sys_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/clk_in_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/rst_n_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/pps_p1_i
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_o
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_valid_o
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/gate_pulse
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/gate_pulse_synced
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/cntr_gate
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/cntr_meas
add wave -noupdate /main/DUT/U_VCXO_Freq_Meter/freq_reg
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {3716002840 fs} 0}
configure wave -namecolwidth 413
WaveRestoreCursors {{Cursor 1} {8145325200 fs} 0}
configure wave -namecolwidth 183
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -97,4 +30,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {3191002840 fs} {4241002840 fs}
WaveRestoreZoom {0 fs} {26250 ns}
files = ["spec_top.vhd", "spec_top.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd"]
fetchto = "../../ip_cores"
fetchto = "../../../ip_cores"
modules = {
"local" : ["../../rtl",
"local" : ["../../../rtl",
"../../../../../wr-repos/wr-hdl/modules/mini_bone",
"../../../../../wr-repos/wr-hdl"],
"svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
......
......@@ -9,11 +9,12 @@
/* fdelay_get_timing_status() return values: */
#define FDELAY_FREE_RUNNING 0x10 /* attached WR core is offline */
#define FDELAY_FREE_RUNNING 0x10 /* local oscillator is free running */
#define FDELAY_WR_OFFLINE 0x8 /* attached WR core is offline */
#define FDELAY_WR_READY 0x1 /* attached WR core is synchronized, we can sync the fine delay core anytime */
#define FDELAY_WR_SYNCING 0x2 /* local oscillator is being synchronized with WR clock */
#define FDELAY_WR_SYNCED 0x4 /* we are synced. */
#define FDELAY_WR_NOT_PRESENT 0x20 /* No WR Core present */
/* fdelay_configure_sync() flags */
......@@ -23,7 +24,7 @@
/* Hardware "handle" structure */
typedef struct fdelay_device
{
/* Base address of the FD core */
/* Base address of the FD core (relative to the beginning of local writel/readl address spaces) */
uint32_t base_addr;
/* Bus-specific readl/writel functions - so the same library can be used both with
......@@ -37,11 +38,10 @@ typedef struct fdelay_device
typedef struct
{
int64_t utc;
int32_t coarse;
int32_t frac;
uint16_t seq_id;
int channel;
int32_t utc; /* TAI seconds */ /* FIXME: replace all UTCs with TAIs or seconds for clarity */
int32_t coarse; /* 125 MHz counter cycles */
int32_t frac; /* Fractional part (<8ns) */
uint16_t seq_id; /* Sequence ID to detect missed timestamps */
} fdelay_time_t;
/*
......@@ -51,24 +51,67 @@ PUBLIC API
*/
fdelay_device_t *fdelay_create_rawrabbit(uint32_t base_addr);
/* Creates a local instance of Fine Delay Core at address base_addr. Returns a non-null fdelay_device_t
card context on success or null if an error occured */
fdelay_device_t *fdelay_create(const char *device);
/* Does the same as above, but for a card accessible via EtherBone/MiniBone.
iface = network interface to which the carrier is connected
mac_addr = MAC address of the EtherBone/MiniBone core
base_addr = base address of the FD core (relative to EB/MB address space) */
fdelay_device_t *fdelay_create_minibone(char *iface, char *mac_addr, uint32_t base_addr);
/* Helper functions - converting FD timestamp format from/to plain picoseconds */
fdelay_time_t fdelay_from_picos(const uint64_t ps);
int64_t fdelay_to_picos(const fdelay_time_t t);
/* Initializes and calibrates the device. 0 = success, negative = error */
int fdelay_init(fdelay_device_t *dev);
/* Disables and releases the resources for a given FD Card */
int fdelay_release(fdelay_device_t *dev);
int fdelay_read(fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many);
/* Returns an explaination of the last error occured on device dev (TBI) */
char *fdelay_strerror(fdelay_device_t *dev);
/* Sets the timing reference for the card (ref source). Currently there are two choices:
- FDELAY_SYNC_LOCAL - use local oscillator
- FDELAY_SYNC_WR - use White Rabbit */
int fdelay_set_timing_reference(fdelay_device_t *dev, int ref_source);
/* Polls the current status of the timing source. Returns a combination of
.... SYNCED flags. wait_mask can enable/disable waiting for a change of
a particular flag or set of flags. For example, calling
fdelay_get_timing_status(dev, FDELAY_WR_SYNCED) will wait until a change of
FDELAY_WR_SYNCED bit. */
int fdelay_get_timing_status(fdelay_device_t *dev, int wait_mask);
/* Configures the trigger input (TDC/Delay modes). enable enables the input,
termination switches on/off the built-in 50 Ohm termination resistor */
int fdelay_configure_trigger(fdelay_device_t *dev, int enable, int termination);
int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int rep_count);
int fdelay_configure_sync(fdelay_device_t *dev, int mode);
int fdelay_update_sync_status(fdelay_device_t *dev);
int fdelay_set_time(fdelay_device_t *dev, const fdelay_time_t t);
int fdelay_configure_pulse_gen(fdelay_device_t *dev, int channel, int enable, fdelay_time_t t_start, int64_t width_ps, int64_t delta_ps, int rep_count);
int fdelay_channel_triggered(fdelay_device_t *dev, int channel);
int fdelay_get_time(fdelay_device_t *dev, fdelay_time_t *t);
/* Configures timestamp buffer capture: enable = TS buffer enabled, channel mask:
channels to time tag (bit 0 = TDC, bits 1..4 = outputs 1..4) */
int fdelay_configure_capture (fdelay_device_t *dev, int enable, int channel_mask);
/* Reads how_many timestamps from the buffer. Blocking */
/* TODO: non-blocking version? */
int fdelay_read (fdelay_device_t *dev, fdelay_time_t *timestamps, int how_many);
/* (delay mode only) Configures output(s) selected in channel_mask to work in delay mode. Delta_ps = spacing between
the rising edges of subsequent pulses. */
int fdelay_configure_delay (fdelay_device_t *dev, int channel_mask, int enable, int64_t delay_ps, int64_t width_ps, int64_t delta_ps, int repeat_count);
/* (pulse mode only) Configures output(s) selected in channel_mask to produce pulse(s) starting at (start) with appropriate width/spacing/repeat_count */
int fdelay_configure_pulse_gen(fdelay_device_t *dev, int channel_mask, int enable, fdelay_time_t start, int64_t width_ps, int64_t delta_ps, int repeat_count);
/* (pulse mode only) Returns non-0 when all of the channels in channel mask have produced their programmed pulses */
int fdelay_outputs_triggered(fdelay_device_t *dev, int channel_mask, int blocking);
#endif
......@@ -883,7 +883,7 @@ int fdelay_init(fdelay_device_t *dev)
if(ds18x_init(dev) < 0)
{
fail(TEST_SPI, "DS18x sensor not detected.");
fail(TEST_SPI, "DS18x sensor not detected.");
dbg("DS18x sensor not detected. Bah!\n");
return -1;
}
......@@ -1336,4 +1336,4 @@ int fd_update_spll(fdelay_device_t *dev)
}
}
#endif
\ No newline at end of file
#endif
#!/usr/bin/python
#!/usr/bin/python2
import sys
import PyQt4
......@@ -70,9 +70,9 @@ def on_chk_wr():
if __name__ == "__main__":
app = QApplication(sys.argv)
if(sys.argv[1] == "1"):
location = "minibone/eth8/00:50:0c:de:bc:f8/0x100000"
location = "minibone/eth0/00:50:0c:de:bc:f8/0x100000"
else:
location = "minibone/eth8/00:50:e4:95:36:f8/0x100000"
location = "minibone/eth0/00:50:e4:95:36:f8/0x100000"
m = MainWindow()
m.show()
......
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