hdl: testing release for V3 hardware

481fc584 · Tomasz Wlostowski · f4ad16ac · 481fc584 · 481fc584 · 481fc584
Commit 481fc584 authored Feb 26, 2012 by Tomasz Wlostowski
22 changed files
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
 files = ["fd_acam_timestamper.vhd",
-         "fd_wbgen2_pkg.vhd",
         "fd_ring_buffer.vhd",
         "fd_ts_adder.vhd",
         "fd_ts_normalizer.vhd",
@@ -10,16 +9,20 @@ files = ["fd_acam_timestamper.vhd",
         "fd_delay_channel_driver.vhd",
         "fd_delay_line_arbiter.vhd",
         "fd_rearm_generator.vhd",
-         "fd_wishbone_slave.vhd",
         "fd_spi_master.vhd",
         "fd_spi_dac_arbiter.vhd",
         "fine_delay_pkg.vhd",
-         "fine_delay_core.vhd"];
+         "fine_delay_core.vhd",
+         "fd_channel_wishbone_slave.vhd",
+         "fd_main_wishbone_slave.vhd",
+         "fd_channel_wbgen2_pkg.vhd",
+         "fd_main_wbgen2_pkg.vhd",
+         "fd_dmtd_insertion_calibrator.vhd",
+         "timing/dmtd_with_deglitcher.vhd",
+				 "timing/hpll_period_detect.vhd"
+    ];

 fetchto = "../ip_cores"

-modules = {
-    "git" :  [
-        "git@ohwr.org:hdl-core-lib/general-cores.git::wishbone_with_adapter" ],
-    "svn" : [ "http://svn.ohwr.org/gn4124-core/branches/hdlmake-compliant/rtl" ]
- };
+modules = { "git" : [ "git@ohwr.org:hdl-core-lib/general-cores.git::proposed_master"] }
+
--- a/hdl/rtl/build_wb.sh
+++ b/hdl/rtl/build_wb.sh
 #!/bin/bash

-~/wbgen2/wishbone-gen/wbgen2 -V fd_wishbone_slave.vhd -H record -p fd_wbgen2_pkg.vhd -K ../include/fine_delay_regs.v -s defines -C fd_core.h -D 1.html fd_wishbone_slave.wb 
\ No newline at end of file
+wbgen2 -V fd_main_wishbone_slave.vhd -H record -p fd_main_wbgen2_pkg.vhd -K ../include/regs/fd_main_regs.vh -s defines -C fd_main_regs.h -D doc/fd_main_regs.html fd_main_wishbone_slave.wb 
+wbgen2 -V fd_channel_wishbone_slave.vhd -H record -p fd_channel_wbgen2_pkg.vhd -K ../include/regs/fd_channel_regs.vh -s defines -C fd_channel_regs.h -D doc/fd_channel_regs.html fd_channel_wishbone_slave.wb 
\ No newline at end of file
--- a/hdl/rtl/fd_acam_timestamp_postprocessor.vhd
+++ b/hdl/rtl/fd_acam_timestamp_postprocessor.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-29
-- Last update: 2011-12-07
+-- Last update: 2012-02-16
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -43,7 +43,8 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

-use work.fd_wbgen2_pkg.all;
+use work.fine_delay_pkg.all;
+use work.fd_main_wbgen2_pkg.all;

 entity fd_acam_timestamp_postprocessor is
  generic(
@@ -58,11 +59,11 @@ entity fd_acam_timestamp_postprocessor is
    ---------------------------------------------------------------------------

    raw_valid_i : in std_logic;
-    raw_utc_i   : in std_logic_vector(31 downto 0);
+    raw_utc_i   : in std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);

    -- "start number" (value of coarse counter, counting at every start pulse of the
    -- TDC, i.e. 125 MHz / 16 = 7.8215 MHz)
-    raw_coarse_i : in std_logic_vector(23 downto 0);
+    raw_coarse_i : in std_logic_vector(c_TIMESTAMP_COARSE_BITS-4-1 downto 0);

    -- raw fractional timestamp generated by ACAM
    raw_frac_i : in std_logic_vector(22 downto 0);
@@ -81,12 +82,12 @@ entity fd_acam_timestamp_postprocessor is
    ---------------------------------------------------------------------------

    tag_valid_o  : out std_logic;
-    tag_utc_o    : out std_logic_vector(31 downto 0);
-    tag_coarse_o : out std_logic_vector(27 downto 0);
+    tag_utc_o    : out std_logic_vector(c_TIMESTAMP_UTC_BITS-1 downto 0);
+    tag_coarse_o : out std_logic_vector(c_TIMESTAMP_COARSE_BITS-1 downto 0);
    tag_frac_o   : out std_logic_vector(g_frac_bits-1 downto 0);

    -- Wishbone regs
-    regs_i : in t_fd_out_registers
+    regs_i : in t_fd_main_out_registers
    );

 end fd_acam_timestamp_postprocessor;
@@ -99,9 +100,9 @@ architecture behavioral of fd_acam_timestamp_postprocessor is

  signal pp_pipe : std_logic_vector(4 downto 0);

-  signal post_tag_coarse         : unsigned(27 downto 0);
+  signal post_tag_coarse         : unsigned(c_TIMESTAMP_COARSE_BITS-1 downto 0);
  signal post_tag_frac           : unsigned(g_frac_bits-1 downto 0);
-  signal post_tag_utc            : unsigned(31 downto 0);
+  signal post_tag_utc            : unsigned(c_TIMESTAMP_UTC_BITS-1 downto 0);
  signal post_frac_multiplied    : signed(c_SCALER_SHIFT + g_frac_bits + 8 downto 0);
  signal post_frac_multiplied_d0 : signed(c_SCALER_SHIFT + g_frac_bits + 8 downto 0);
  signal post_frac_start_adj     : signed(22 downto 0);

--- a/hdl/rtl/fd_acam_timestamper.vhd
+++ b/hdl/rtl/fd_acam_timestamper.vhd
--- a/hdl/rtl/fd_channel_wbgen2_pkg.vhd
+++ b/hdl/rtl/fd_channel_wbgen2_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Fine Delay Channel WB Slave
+---------------------------------------------------------------------------------------
+-- File           : fd_channel_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
+-- Created        : Sun Feb 26 22:33:04 2012
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package fd_channel_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_fd_channel_in_registers is record
+    dcr_pg_arm_i                             : std_logic;
+    dcr_pg_trig_i                            : std_logic;
+    dcr_upd_done_i                           : std_logic;
+    end record;
+  
+  constant c_fd_channel_in_registers_init_value: t_fd_channel_in_registers := (
+    dcr_pg_arm_i => '0',
+    dcr_pg_trig_i => '0',
+    dcr_upd_done_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_fd_channel_out_registers is record
+      dcr_enable_o                             : std_logic;
+      dcr_mode_o                               : std_logic;
+      dcr_pg_arm_o                             : std_logic;
+      dcr_pg_arm_load_o                        : std_logic;
+      dcr_update_o                             : std_logic;
+      dcr_force_dly_o                          : std_logic;
+      dcr_no_fine_o                            : std_logic;
+      frr_o                                    : std_logic_vector(9 downto 0);
+      u_starth_o                               : std_logic_vector(7 downto 0);
+      u_startl_o                               : std_logic_vector(31 downto 0);
+      c_start_o                                : std_logic_vector(27 downto 0);
+      f_start_o                                : std_logic_vector(11 downto 0);
+      u_endh_o                                 : std_logic_vector(7 downto 0);
+      u_endl_o                                 : std_logic_vector(31 downto 0);
+      c_end_o                                  : std_logic_vector(27 downto 0);
+      f_end_o                                  : std_logic_vector(11 downto 0);
+      u_delta_o                                : std_logic_vector(3 downto 0);
+      c_delta_o                                : std_logic_vector(27 downto 0);
+      f_delta_o                                : std_logic_vector(11 downto 0);
+      rcr_rep_cnt_o                            : std_logic_vector(15 downto 0);
+      rcr_cont_o                               : std_logic;
+      end record;
+    
+    constant c_fd_channel_out_registers_init_value: t_fd_channel_out_registers := (
+      dcr_enable_o => '0',
+      dcr_mode_o => '0',
+      dcr_pg_arm_o => '0',
+      dcr_pg_arm_load_o => '0',
+      dcr_update_o => '0',
+      dcr_force_dly_o => '0',
+      dcr_no_fine_o => '0',
+      frr_o => (others => '0'),
+      u_starth_o => (others => '0'),
+      u_startl_o => (others => '0'),
+      c_start_o => (others => '0'),
+      f_start_o => (others => '0'),
+      u_endh_o => (others => '0'),
+      u_endl_o => (others => '0'),
+      c_end_o => (others => '0'),
+      f_end_o => (others => '0'),
+      u_delta_o => (others => '0'),
+      c_delta_o => (others => '0'),
+      f_delta_o => (others => '0'),
+      rcr_rep_cnt_o => (others => '0'),
+      rcr_cont_o => '0'
+      );
+    function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+end package;
+
+package body fd_channel_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if(x = 'X' or x = 'U') then
+return '0';
+else
+return x;
+end if; 
+end function;
+function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is
+variable tmp: t_fd_channel_in_registers;
+begin
+tmp.dcr_pg_arm_i := left.dcr_pg_arm_i or right.dcr_pg_arm_i;
+tmp.dcr_pg_trig_i := left.dcr_pg_trig_i or right.dcr_pg_trig_i;
+tmp.dcr_upd_done_i := left.dcr_upd_done_i or right.dcr_upd_done_i;
+return tmp;
+end function;
+end package body;
--- a/hdl/rtl/fd_channel_wishbone_slave.vhd
+++ b/hdl/rtl/fd_channel_wishbone_slave.vhd
--- a/hdl/rtl/fd_channel_wishbone_slave.wb
+++ b/hdl/rtl/fd_channel_wishbone_slave.wb
--- a/hdl/rtl/fd_csync_generator.vhd
+++ b/hdl/rtl/fd_csync_generator.vhd
--- a/hdl/rtl/fd_delay_channel_driver.vhd
+++ b/hdl/rtl/fd_delay_channel_driver.vhd
--- a/hdl/rtl/fd_delay_line_arbiter.vhd
+++ b/hdl/rtl/fd_delay_line_arbiter.vhd
+-----------------------------------------------------------------------------
+-- Title      : SY89295U 4-input arbitration unit
+-- Project    : Fine Delay FMC (fmc-delay-1ns-4cha)
+-------------------------------------------------------------------------------
+-- File       : fd_delay_line_arbiter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Created    : 2011-08-24
+-- Last update: 2012-02-26
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Multiplexes access from 4 delay generators to a single shared
+-- bus driving the SY89295U fine delay line chips.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-08-24  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -9,15 +49,21 @@ entity fd_delay_line_arbiter is
    clk_ref_i : in std_logic;
    rst_n_i   : in std_logic;

+    -- when load_i(X) == 1, delay_valX_i contains a new setpoint for delay line
+    -- X and requests reprogramming the delay line
    load_i : in  std_logic_vector(3 downto 0);
+    -- 1: acknowledge of the request above
    done_o : out std_logic_vector(3 downto 0);

+    -- tap delay values for all channels
    delay_val0_i : in std_logic_vector(9 downto 0);
    delay_val1_i : in std_logic_vector(9 downto 0);
    delay_val2_i : in std_logic_vector(9 downto 0);
    delay_val3_i : in std_logic_vector(9 downto 0);

+    -- SY89295U outputs: delay value ...
    delay_val_o : out std_logic_vector(9 downto 0);
+    -- ... and latch enable (active low).
    delay_len_o : out std_logic_vector(3 downto 0)

    );
@@ -63,7 +109,6 @@ begin  -- behavioral

          if(arb_sreg(3*i+1) = '1') then
            delay_val_reg <= delay_vec(i);
--            delay_len_reg(i) <= '0';
            done_o(i)     <= '0';
          end if;

@@ -76,7 +121,6 @@ begin  -- behavioral

        end loop;  -- i in 0 to 3

--        done_o      <= done_reg;
        delay_len_o <= delay_len_reg;
        delay_val_o <= delay_val_reg;
      end if;

--- a/hdl/rtl/fd_dmtd_insertion_calibrator.vhd
+++ b/hdl/rtl/fd_dmtd_insertion_calibrator.vhd
--- a/hdl/rtl/fd_wbgen2_pkg.vhd
+++ b/hdl/rtl/fd_wbgen2_pkg.vhd
--- a/hdl/rtl/fd_main_wishbone_slave.vhd
+++ b/hdl/rtl/fd_main_wishbone_slave.vhd
--- a/hdl/rtl/fd_main_wishbone_slave.wb
+++ b/hdl/rtl/fd_main_wishbone_slave.wb
--- a/hdl/rtl/fd_reset_generator.vhd
+++ b/hdl/rtl/fd_reset_generator.vhd
--- a/hdl/rtl/fd_ring_buffer.vhd
+++ b/hdl/rtl/fd_ring_buffer.vhd
--- a/hdl/rtl/fd_spi_dac_arbiter.vhd
+++ b/hdl/rtl/fd_spi_dac_arbiter.vhd
--- a/hdl/rtl/fd_spi_master.vhd
+++ b/hdl/rtl/fd_spi_master.vhd
--- a/hdl/rtl/fd_timestamper_stat_unit.vhd
+++ b/hdl/rtl/fd_timestamper_stat_unit.vhd
--- a/hdl/rtl/fd_ts_adder.vhd
+++ b/hdl/rtl/fd_ts_adder.vhd
--- a/hdl/rtl/fine_delay_core.vhd
+++ b/hdl/rtl/fine_delay_core.vhd
--- a/hdl/rtl/fine_delay_pkg.vhd
+++ b/hdl/rtl/fine_delay_pkg.vhd