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FMC DEL 1ns 4cha
Commits
6f48bd55
Commit
6f48bd55
authored
Feb 26, 2012
by
Tomasz Wlostowski
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hdl: assignment size bug fixed
parent
354391a9
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13 changed files
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347 additions
and
1 deletion
+347
-1
fd_dmtd_insertion_calibrator.vhd
hdl/rtl/fd_dmtd_insertion_calibrator.vhd
+1
-1
Manifest.py
hdl/syn/spec/non_wr/Manifest.py
+0
-0
spec_fine_delay.xise
hdl/syn/spec/non_wr/spec_fine_delay.xise
+0
-0
Manifest.py
hdl/top/spec/non_wr/Manifest.py
+0
-0
spec_serial_dac.vhd
hdl/top/spec/non_wr/spec_serial_dac.vhd
+0
-0
spec_serial_dac_arb.vhd
hdl/top/spec/non_wr/spec_serial_dac_arb.vhd
+0
-0
spec_top.ucf
hdl/top/spec/non_wr/spec_top.ucf
+0
-0
spec_top.vhd
hdl/top/spec/non_wr/spec_top.vhd
+0
-0
Manifest.py
hdl/top/spec/wr/Manifest.py
+0
-0
spec_serial_dac.vhd
hdl/top/spec/wr/spec_serial_dac.vhd
+190
-0
spec_serial_dac_arb.vhd
hdl/top/spec/wr/spec_serial_dac_arb.vhd
+156
-0
spec_top.ucf
hdl/top/spec/wr/spec_top.ucf
+0
-0
spec_top.vhd
hdl/top/spec/wr/spec_top.vhd
+0
-0
No files found.
hdl/rtl/fd_dmtd_insertion_calibrator.vhd
View file @
6f48bd55
...
...
@@ -346,7 +346,7 @@ begin -- rtl
regs_o
.
calr_dmtd_tag_rdy_i
<=
'0'
;
else
if
(
new_edge_p
=
'1'
)
then
regs_o
.
calr_dmtd_tag_i
<=
std_logic_vector
(
tag_int
);
regs_o
.
calr_dmtd_tag_i
<=
std_logic_vector
(
tag_int
(
22
downto
0
)
);
regs_o
.
calr_dmtd_tag_rdy_i
<=
'1'
;
elsif
(
calr_rd_ack_i
=
'1'
)
then
regs_o
.
calr_dmtd_tag_rdy_i
<=
'0'
;
...
...
hdl/syn/spec
_1_1
/Manifest.py
→
hdl/syn/spec
/non_wr
/Manifest.py
View file @
6f48bd55
File moved
hdl/syn/spec
_1_1
/spec_fine_delay.xise
→
hdl/syn/spec
/non_wr
/spec_fine_delay.xise
View file @
6f48bd55
File moved
hdl/top/spec
_1_1
/Manifest.py
→
hdl/top/spec
/non_wr
/Manifest.py
View file @
6f48bd55
File moved
hdl/top/spec
_wr_demo
/spec_serial_dac.vhd
→
hdl/top/spec
/non_wr
/spec_serial_dac.vhd
View file @
6f48bd55
File moved
hdl/top/spec
_wr_demo
/spec_serial_dac_arb.vhd
→
hdl/top/spec
/non_wr
/spec_serial_dac_arb.vhd
View file @
6f48bd55
File moved
hdl/top/spec
_1_1
/spec_top.ucf
→
hdl/top/spec
/non_wr
/spec_top.ucf
View file @
6f48bd55
File moved
hdl/top/spec
_1_1
/spec_top.vhd
→
hdl/top/spec
/non_wr
/spec_top.vhd
View file @
6f48bd55
File moved
hdl/top/spec
_wr_demo
/Manifest.py
→
hdl/top/spec
/wr
/Manifest.py
View file @
6f48bd55
File moved
hdl/top/spec/wr/spec_serial_dac.vhd
0 → 100644
View file @
6f48bd55
-------------------------------------------------------------------------------
-- Title : Serial DAC interface
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : serial_dac.vhd
-- Author : paas, slayer
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-05-10
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
-------------------------------------------------------------------------------
-- Revisions :1
-- Date Version Author Description
-- 2009-01-24 1.0 paas Created
-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch
-------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
IEEE
.
numeric_std
.
all
;
entity
spec_serial_dac
is
generic
(
g_num_data_bits
:
integer
:
=
16
;
g_num_extra_bits
:
integer
:
=
8
;
g_num_cs_select
:
integer
:
=
2
);
port
(
-- clock & reset
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- channel 1 value and value load strobe
value_i
:
in
std_logic_vector
(
g_num_data_bits
-1
downto
0
);
cs_sel_i
:
in
std_logic_vector
(
g_num_cs_select
-1
downto
0
);
load_i
:
in
std_logic
;
-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
sclk_divsel_i
:
in
std_logic_vector
(
2
downto
0
);
-- DAC I/F
dac_cs_n_o
:
out
std_logic_vector
(
g_num_cs_select
-1
downto
0
);
dac_sclk_o
:
out
std_logic
;
dac_sdata_o
:
out
std_logic
;
xdone_o
:
out
std_logic
);
end
spec_serial_dac
;
architecture
syn
of
spec_serial_dac
is
signal
divider
:
unsigned
(
11
downto
0
);
signal
dataSh
:
std_logic_vector
(
g_num_data_bits
+
g_num_extra_bits
-1
downto
0
);
signal
bitCounter
:
std_logic_vector
(
g_num_data_bits
+
g_num_extra_bits
+
1
downto
0
);
signal
endSendingData
:
std_logic
;
signal
sendingData
:
std_logic
;
signal
iDacClk
:
std_logic
;
signal
iValidValue
:
std_logic
;
signal
divider_muxed
:
std_logic
;
signal
cs_sel_reg
:
std_logic_vector
(
g_num_cs_select
-1
downto
0
);
begin
select_divider
:
process
(
divider
,
sclk_divsel_i
)
begin
-- process
case
sclk_divsel_i
is
when
"000"
=>
divider_muxed
<=
divider
(
1
);
-- sclk = clk_i/8
when
"001"
=>
divider_muxed
<=
divider
(
2
);
-- sclk = clk_i/16
when
"010"
=>
divider_muxed
<=
divider
(
3
);
-- sclk = clk_i/32
when
"011"
=>
divider_muxed
<=
divider
(
4
);
-- sclk = clk_i/64
when
"100"
=>
divider_muxed
<=
divider
(
5
);
-- sclk = clk_i/128
when
"101"
=>
divider_muxed
<=
divider
(
6
);
-- sclk = clk_i/256
when
"110"
=>
divider_muxed
<=
divider
(
7
);
-- sclk = clk_i/512
when
"111"
=>
divider_muxed
<=
divider
(
8
);
-- sclk = clk_i/1024
when
others
=>
null
;
end
case
;
end
process
;
iValidValue
<=
load_i
;
process
(
clk_i
,
rst_n_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
sendingData
<=
'0'
;
else
if
iValidValue
=
'1'
and
sendingData
=
'0'
then
sendingData
<=
'1'
;
elsif
endSendingData
=
'1'
then
sendingData
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
iValidValue
=
'1'
then
divider
<=
(
others
=>
'0'
);
elsif
sendingData
=
'1'
then
if
(
divider_muxed
=
'1'
)
then
divider
<=
(
others
=>
'0'
);
else
divider
<=
divider
+
1
;
end
if
;
elsif
endSendingData
=
'1'
then
divider
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
process
;
process
(
clk_i
,
rst_n_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
iDacClk
<=
'1'
;
-- 0
else
if
iValidValue
=
'1'
then
iDacClk
<=
'1'
;
-- 0
elsif
divider_muxed
=
'1'
then
iDacClk
<=
not
(
iDacClk
);
elsif
endSendingData
=
'1'
then
iDacClk
<=
'1'
;
-- 0
end
if
;
end
if
;
end
if
;
end
process
;
process
(
clk_i
,
rst_n_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
dataSh
<=
(
others
=>
'0'
);
else
if
iValidValue
=
'1'
and
sendingData
=
'0'
then
cs_sel_reg
<=
cs_sel_i
;
dataSh
(
g_num_data_bits
-1
downto
0
)
<=
value_i
;
dataSh
(
dataSh
'left
downto
g_num_data_bits
)
<=
(
others
=>
'0'
);
elsif
sendingData
=
'1'
and
divider_muxed
=
'1'
and
iDacClk
=
'0'
then
dataSh
(
0
)
<=
dataSh
(
dataSh
'left
);
dataSh
(
dataSh
'left
downto
1
)
<=
dataSh
(
dataSh
'left
-
1
downto
0
);
end
if
;
end
if
;
end
if
;
end
process
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
iValidValue
=
'1'
and
sendingData
=
'0'
then
bitCounter
(
0
)
<=
'1'
;
bitCounter
(
bitCounter
'left
downto
1
)
<=
(
others
=>
'0'
);
elsif
sendingData
=
'1'
and
to_integer
(
divider
)
=
0
and
iDacClk
=
'1'
then
bitCounter
(
0
)
<=
'0'
;
bitCounter
(
bitCounter
'left
downto
1
)
<=
bitCounter
(
bitCounter
'left
-
1
downto
0
);
end
if
;
end
if
;
end
process
;
endSendingData
<=
bitCounter
(
bitCounter
'left
);
xdone_o
<=
not
SendingData
;
dac_sdata_o
<=
dataSh
(
dataSh
'left
);
gen_cs_out
:
for
i
in
0
to
g_num_cs_select
-1
generate
dac_cs_n_o
(
i
)
<=
not
(
sendingData
)
or
(
not
cs_sel_reg
(
i
));
end
generate
gen_cs_out
;
dac_sclk_o
<=
iDacClk
;
end
syn
;
hdl/top/spec/wr/spec_serial_dac_arb.vhd
0 → 100644
View file @
6f48bd55
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
spec_serial_dac_arb
is
generic
(
g_invert_sclk
:
boolean
;
g_num_extra_bits
:
integer
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
val1_i
:
in
std_logic_vector
(
15
downto
0
);
load1_i
:
in
std_logic
;
val2_i
:
in
std_logic_vector
(
15
downto
0
);
load2_i
:
in
std_logic
;
dac_cs_n_o
:
out
std_logic_vector
(
1
downto
0
);
dac_clr_n_o
:
out
std_logic
;
dac_sclk_o
:
out
std_logic
;
dac_din_o
:
out
std_logic
);
end
spec_serial_dac_arb
;
architecture
behavioral
of
spec_serial_dac_arb
is
component
spec_serial_dac
generic
(
g_num_data_bits
:
integer
;
g_num_extra_bits
:
integer
;
g_num_cs_select
:
integer
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
value_i
:
in
std_logic_vector
(
g_num_data_bits
-1
downto
0
);
cs_sel_i
:
in
std_logic_vector
(
g_num_cs_select
-1
downto
0
);
load_i
:
in
std_logic
;
sclk_divsel_i
:
in
std_logic_vector
(
2
downto
0
);
dac_cs_n_o
:
out
std_logic_vector
(
g_num_cs_select
-1
downto
0
);
dac_sclk_o
:
out
std_logic
;
dac_sdata_o
:
out
std_logic
;
xdone_o
:
out
std_logic
);
end
component
;
signal
d1
,
d2
:
std_logic_vector
(
15
downto
0
);
signal
d1_ready
,
d2_ready
:
std_logic
;
signal
dac_data
:
std_logic_vector
(
15
downto
0
);
signal
dac_load
:
std_logic
;
signal
dac_cs_sel
:
std_logic_vector
(
1
downto
0
);
signal
dac_done
:
std_logic
;
signal
dac_sclk_int
:
std_logic
;
type
t_state
is
(
WAIT_DONE
,
LOAD_DAC
,
WAIT_DATA
);
signal
state
:
t_state
;
signal
trig0
:
std_logic_vector
(
31
downto
0
);
signal
trig1
:
std_logic_vector
(
31
downto
0
);
signal
trig2
:
std_logic_vector
(
31
downto
0
);
signal
trig3
:
std_logic_vector
(
31
downto
0
);
signal
CONTROL0
:
std_logic_vector
(
35
downto
0
);
begin
-- behavioral
dac_clr_n_o
<=
'1'
;
U_DAC
:
spec_serial_dac
generic
map
(
g_num_data_bits
=>
16
,
g_num_extra_bits
=>
g_num_extra_bits
,
g_num_cs_select
=>
2
)
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
value_i
=>
dac_data
,
cs_sel_i
=>
dac_cs_sel
,
load_i
=>
dac_load
,
sclk_divsel_i
=>
"001"
,
dac_cs_n_o
=>
dac_cs_n_o
,
dac_sclk_o
=>
dac_sclk_int
,
dac_sdata_o
=>
dac_din_o
,
xdone_o
=>
dac_done
);
p_drive_sclk
:
process
(
dac_sclk_int
)
begin
if
(
g_invert_sclk
)
then
dac_sclk_o
<=
not
dac_sclk_int
;
else
dac_sclk_o
<=
dac_sclk_int
;
end
if
;
end
process
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
d1
<=
(
others
=>
'0'
);
d1_ready
<=
'0'
;
d2
<=
(
others
=>
'0'
);
d2_ready
<=
'0'
;
dac_load
<=
'0'
;
dac_cs_sel
<=
(
others
=>
'0'
);
state
<=
WAIT_DATA
;
else
if
(
load1_i
=
'1'
or
load2_i
=
'1'
)
then
if
(
load1_i
=
'1'
)
then
d1_ready
<=
'1'
;
d1
<=
val1_i
;
end
if
;
if
(
load2_i
=
'1'
)
then
d2_ready
<=
'1'
;
d2
<=
val2_i
;
end
if
;
else
case
state
is
when
WAIT_DATA
=>
if
(
d1_ready
=
'1'
)
then
dac_cs_sel
<=
"01"
;
dac_data
<=
d1
;
dac_load
<=
'1'
;
d1_ready
<=
'0'
;
state
<=
LOAD_DAC
;
elsif
(
d2_ready
=
'1'
)
then
dac_cs_sel
<=
"10"
;
dac_data
<=
d2
;
dac_load
<=
'1'
;
d2_ready
<=
'0'
;
state
<=
LOAD_DAC
;
end
if
;
when
LOAD_DAC
=>
dac_load
<=
'0'
;
state
<=
WAIT_DONE
;
when
WAIT_DONE
=>
if
(
dac_done
=
'1'
)
then
state
<=
WAIT_DATA
;
end
if
;
when
others
=>
null
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
;
end
behavioral
;
hdl/top/spec
_wr_demo
/spec_top.ucf
→
hdl/top/spec
/wr
/spec_top.ucf
View file @
6f48bd55
File moved
hdl/top/spec
_wr_demo
/spec_top.vhd
→
hdl/top/spec
/wr
/spec_top.vhd
View file @
6f48bd55
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