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FMC DEL 1ns 4cha
Commit 60d30547 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/fd_main_wishbone_slave: added DBGOUT register for Peltier PWM control

parent 2359142a
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Showing with 63 additions and 39 deletions
hdl/rtl/doc/fd_main_regs.html
View file @ 60d30547
......@@ -3073,6 +3073,23 @@ fd_main_i2cr_dbg_i[3:0]
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fd_main_i2cr_dbgout_o[11:0]
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......@@ -10239,17 +10256,17 @@ I2CR
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<td style="border: solid 1px black;" colspan=4 class="td_field">
DBGOUT[11:8]
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......@@ -10281,29 +10298,29 @@ I2CR
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DBGOUT[7:0]
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......@@ -10377,6 +10394,9 @@ SDA_IN
<li><b>
DBG
</b>[<i>read-only</i>]: Debug in
<li><b>
DBGOUT
</b>[<i>read/write</i>]: Debug out
</ul>
<a name="EIC_IDR"></a>
<h3><a name="sect_3_28">3.28. Interrupt disable register</a></h3>
......
hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ 60d30547
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Sun Feb 26 22:33:04 2012
-- Created : Wed Feb 29 12:04:02 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -149,6 +149,7 @@ package fd_main_wbgen2_pkg is
tsbir_threshold_o : std_logic_vector(11 downto 0);
i2cr_scl_out_o : std_logic;
i2cr_sda_out_o : std_logic;
i2cr_dbgout_o : std_logic_vector(11 downto 0);
end record;
constant c_fd_main_out_registers_init_value: t_fd_main_out_registers := (
......@@ -205,7 +206,8 @@ package fd_main_wbgen2_pkg is
tsbir_timeout_o => (others => '0'),
tsbir_threshold_o => (others => '0'),
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0'
i2cr_sda_out_o => '0',
i2cr_dbgout_o => (others => '0')
);
function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ 60d30547
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Sun Feb 26 22:33:04 2012
-- Created : Wed Feb 29 12:04:02 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -237,6 +237,7 @@ signal fd_main_tsbir_timeout_int : std_logic_vector(9 downto 0);
signal fd_main_tsbir_threshold_int : std_logic_vector(11 downto 0);
signal fd_main_i2cr_scl_out_int : std_logic ;
signal fd_main_i2cr_sda_out_int : std_logic ;
signal fd_main_i2cr_dbgout_int : std_logic_vector(11 downto 0);
signal eic_idr_int : std_logic_vector(2 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(2 downto 0);
......@@ -375,6 +376,7 @@ begin
advance_rbuf_o <= '0';
fd_main_i2cr_scl_out_int <= '0';
fd_main_i2cr_sda_out_int <= '0';
fd_main_i2cr_dbgout_int <= "000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -1099,24 +1101,14 @@ begin
if (wb_we_i = '1') then
fd_main_i2cr_scl_out_int <= wrdata_reg(0);
fd_main_i2cr_sda_out_int <= wrdata_reg(1);
fd_main_i2cr_dbgout_int <= wrdata_reg(19 downto 8);
end if;
rddata_reg(0) <= fd_main_i2cr_scl_out_int;
rddata_reg(1) <= fd_main_i2cr_sda_out_int;
rddata_reg(2) <= regs_i.i2cr_scl_in_i;
rddata_reg(3) <= regs_i.i2cr_sda_in_i;
rddata_reg(7 downto 4) <= regs_i.i2cr_dbg_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(19 downto 8) <= fd_main_i2cr_dbgout_int;
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
......@@ -1980,6 +1972,8 @@ begin
-- SCL Line in
-- SDA Line in
-- Debug in
-- Debug out
regs_o.i2cr_dbgout_o <= fd_main_i2cr_dbgout_int;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
......
hdl/rtl/fd_main_wishbone_slave.wb
View file @ 60d30547
......@@ -895,6 +895,14 @@ write 0: DMTD pattern generation disabled.";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Debug out";
prefix = "DBGOUT";
type = SLV;
size = 12;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......
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