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FMC DEL 1ns 2cha
Commit b97eee85 authored by Tom Levens's avatar Tom Levens
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Remove unused ports in instantiation of base

parent 995c4865
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Showing with 23 additions and 159 deletions
hdl/top/spec/spec_top_ffpg.vhd
View file @ b97eee85
......@@ -242,10 +242,7 @@ architecture top of spec_top_ffpg is
-- Clocks & reset
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal rst_sys_62m5_n : std_logic := '0';
signal rst_ref_125m_n : std_logic := '0';
-- Wishbone
signal master_wb_out : t_wishbone_master_out;
......@@ -285,18 +282,16 @@ begin
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => False,
g_WITH_ONEWIRE => True,
g_WITH_SPI => True,
g_WITH_WR => False,
g_WITH_DDR => False,
g_DDR_DATA_SIZE => 64,
g_APP_OFFSET => x"0000_4000",
g_NUM_USER_IRQ => 0,
g_DPRAM_INITF => "",
g_AUX_CLKS => 0,
g_FABRIC_IFACE => open,
g_SIMULATION => f_int2bool(g_SIMULATION))
g_WITH_VIC => FALSE,
g_WITH_ONEWIRE => TRUE,
g_WITH_SPI => TRUE,
g_WITH_WR => FALSE,
g_WITH_DDR => FALSE,
g_APP_OFFSET => x"0000_4000",
g_NUM_USER_IRQ => 0,
g_SIMULATION => f_int2bool(g_SIMULATION),
g_VERBOSE => g_VERBOSE
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
......@@ -334,8 +329,6 @@ begin
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
......@@ -354,52 +347,11 @@ begin
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr_a_o => open,
ddr_ba_o => open,
ddr_cas_n_o => open,
ddr_ck_n_o => open,
ddr_ck_p_o => open,
ddr_cke_o => open,
ddr_dq_b => open,
ddr_ldm_o => open,
ddr_ldqs_n_b => open,
ddr_ldqs_p_b => open,
ddr_odt_o => open,
ddr_ras_n_o => open,
ddr_reset_n_o => open,
ddr_rzq_b => open,
ddr_udm_o => open,
ddr_udqs_n_b => open,
ddr_udqs_p_b => open,
ddr_we_n_o => open,
ddr_dma_clk_i => clk_ref_125m,
ddr_dma_rst_n_i => rst_ref_125m_n,
ddr_dma_wb_cyc_i => '0',
ddr_dma_wb_stb_i => '0',
ddr_dma_wb_adr_i => x"0000_0000",
ddr_dma_wb_sel_i => x"00",
ddr_dma_wb_we_i => '0',
ddr_dma_wb_dat_i => (63 downto 0 => '0'),
ddr_dma_wb_ack_o => open,
ddr_dma_wb_stall_o => open,
ddr_dma_wb_dat_o => open,
ddr_wr_fifo_empty_o => open,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
clk_125m_ref_o => clk_ref_125m,
rst_125m_ref_n_o => rst_ref_125m_n,
clk_125m_ref_o => open,
rst_125m_ref_n_o => open,
irq_user_i => "",
wrf_src_o => open,
wrf_src_i => open,
wrf_snk_o => open,
wrf_snk_i => open,
tm_link_up_o => open,
tm_time_valid_o => open,
tm_tai_o => open,
tm_cycles_o => open,
pps_p_o => open,
pps_led_o => open,
link_ok_o => open,
app_wb_o => master_wb_out,
app_wb_i => master_wb_in
);
......
hdl/top/svec/svec_top_ffpg.vhd
View file @ b97eee85
......@@ -319,7 +319,7 @@ architecture top of svec_top_ffpg is
-- Clocks & reset
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_sys_62m5_n : std_logic := '0';
-- Wishbone
signal master_wb_out : t_wishbone_master_out;
......@@ -370,21 +370,16 @@ begin
inst_svec_base: entity work.svec_base_wr
generic map (
g_with_vic => False,
g_with_onewire => True,
g_with_spi => True,
g_with_wr => False,
g_with_ddr4 => False,
g_with_ddr5 => False,
g_app_offset => x"0000_4000",
g_num_user_irq => 0,
g_dpram_initf => "",
g_fabric_iface => open,
g_streamers_op_mode => open,
g_tx_streamer_params => open,
g_rx_streamer_params => open,
g_simulation => g_SIMULATION,
g_verbose => g_VERBOSE
g_WITH_VIC => FALSE,
g_WITH_ONEWIRE => TRUE,
g_WITH_SPI => TRUE,
g_WITH_WR => FALSE,
g_WITH_DDR4 => FALSE,
g_WITH_DDR5 => FALSE,
g_APP_OFFSET => x"0000_4000",
g_NUM_USER_IRQ => 0,
g_SIMULATION => g_SIMULATION,
g_VERBOSE => g_VERBOSE
)
port map (
rst_n_i => rst_n_i,
......@@ -450,95 +445,12 @@ begin
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr4_a_o => open,
ddr4_ba_o => open,
ddr4_cas_n_o => open,
ddr4_ck_n_o => open,
ddr4_ck_p_o => open,
ddr4_cke_o => open,
ddr4_dq_b => open,
ddr4_ldm_o => open,
ddr4_ldqs_n_b => open,
ddr4_ldqs_p_b => open,
ddr4_odt_o => open,
ddr4_ras_n_o => open,
ddr4_reset_n_o => open,
ddr4_rzq_b => open,
ddr4_udm_o => open,
ddr4_udqs_n_b => open,
ddr4_udqs_p_b => open,
ddr4_we_n_o => open,
ddr5_a_o => open,
ddr5_ba_o => open,
ddr5_cas_n_o => open,
ddr5_ck_n_o => open,
ddr5_ck_p_o => open,
ddr5_cke_o => open,
ddr5_dq_b => open,
ddr5_ldm_o => open,
ddr5_ldqs_n_b => open,
ddr5_ldqs_p_b => open,
ddr5_odt_o => open,
ddr5_ras_n_o => open,
ddr5_reset_n_o => open,
ddr5_rzq_b => open,
ddr5_udm_o => open,
ddr5_udqs_n_b => open,
ddr5_udqs_p_b => open,
ddr5_we_n_o => open,
pcbrev_i => pcbrev_i,
ddr4_clk_i => clk_sys_62m5,
ddr4_rst_n_i => rst_sys_62m5_n,
ddr4_wb_i.cyc => '0',
ddr4_wb_i.stb => '0',
ddr4_wb_i.adr => x"0000_0000",
ddr4_wb_i.sel => x"00",
ddr4_wb_i.we => '0',
ddr4_wb_i.dat => (63 downto 0 => '0'),
ddr4_wb_o => open,
ddr5_clk_i => clk_sys_62m5,
ddr5_rst_n_i => rst_sys_62m5_n,
ddr5_wb_i.cyc => '0',
ddr5_wb_i.stb => '0',
ddr5_wb_i.adr => x"0000_0000",
ddr5_wb_i.sel => x"00",
ddr5_wb_i.we => '0',
ddr5_wb_i.dat => (63 downto 0 => '0'),
ddr5_wb_o => open,
ddr4_wr_fifo_empty_o => open,
ddr5_wr_fifo_empty_o => open,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => open,
rst_ref_125m_n_o => open,
irq_user_i => "",
wrf_src_o => open,
wrf_src_i => open,
wrf_snk_o => open,
wrf_snk_i => open,
wrs_tx_data_i => open,
wrs_tx_valid_i => open,
wrs_tx_dreq_o => open,
wrs_tx_last_i => open,
wrs_tx_flush_i => open,
wrs_tx_cfg_i => open,
wrs_rx_first_o => open,
wrs_rx_last_o => open,
wrs_rx_data_o => open,
wrs_rx_valid_o => open,
wrs_rx_dreq_i => open,
wrs_rx_cfg_i => open,
wb_eth_master_o => open,
wb_eth_master_i => open,
tm_link_up_o => open,
tm_time_valid_o => open,
tm_tai_o => open,
tm_cycles_o => open,
pps_p_o => open,
pps_led_o => open,
link_ok_o => open,
led_link_o => open,
led_act_o => open,
app_wb_o => master_wb_out,
app_wb_i => master_wb_in
);
......
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