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FMC DEL 1ns 2cha
Commit 995c4865 authored by Tom Levens's avatar Tom Levens
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Add SPEC top level and synthesis

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.gitmodules
View file @ 995c4865
......@@ -15,3 +15,9 @@
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = https://ohwr.org/project/gn4124-core.git
HISTORY.txt
View file @ 995c4865
......@@ -2,6 +2,7 @@ v2.0.0, 2023-02-24
migrate to latest SVEC base design
migrate to hdlmake build chain
add EDGE driver
add SPEC as a platform
v1.4.2, 2023-02-23
modify pulse generator FSM
......
hdl/ffpg/rtl/FfpgCore.vhd
View file @ 995c4865
......@@ -43,7 +43,8 @@ use work.wishbone_pkg.all;
entity FfpgCore is
generic (
g_ClkFrequency: positive -- input clock frequency in Hz
g_ClkFrequency: positive; -- input clock frequency in Hz
g_Version: std_logic_vector(31 downto 0)
);
port (
-- Wishbone connection
......@@ -199,7 +200,8 @@ begin
cFfpgSlave: entity work.FfpgSlave(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
g_ClkFrequency => g_ClkFrequency,
g_Version => g_Version
)
port map (
Clk_ik => Clk_ik,
......
hdl/ffpg/rtl/FfpgCoreWrapper.vhd 0 → 100644
View file @ 995c4865
-------------------------------------------------------------------------------
-- Title : FFPG core wrapper
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : FfpgCoreWrapper.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-06-28
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Wrapper of the FFPG core with platform specifc primitives.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.FfpgPkg.all;
use work.wishbone_pkg.all;
entity FfpgCoreWrapper is
generic (
g_ClkFrequency: positive; -- input clock frequency in Hz
g_Version: std_logic_vector(31 downto 0)
);
port (
-- Wishbone connection
Clk_ik: in std_logic;
Reset_ira: in std_logic; -- synchronized locally for better timing
Wb_i: in t_wishbone_slave_in;
Wb_o: out t_wishbone_slave_out;
--- FMC interface
-- clock
ClkIn0P_ik: in std_logic; -- 1 MHz <= f_ClkIn0_ik <= 204 MHz
ClkIn0N_ik: in std_logic; -- 1 MHz <= f_ClkIn0_ik <= 204 MHz
-- DACs
TriggerDac_o: out t_Ad5600Interface;
VcxoDac_o: out t_Ad5600Interface;
-- output enable
Ch1OutputEnable_o: out std_logic;
Ch2OutputEnable_o: out std_logic;
-- delay configuration
DelayValue_ob: out unsigned(9 downto 0);
Ch1SetLe_on: out std_logic;
Ch1ResLe_on: out std_logic;
Ch2SetLe_on: out std_logic;
Ch2ResLe_on: out std_logic;
--
Ch1SetP_o: out std_logic;
Ch1SetN_o: out std_logic;
Ch1ResP_o: out std_logic;
Ch1ResN_o: out std_logic;
Ch2SetP_o: out std_logic;
Ch2SetN_o: out std_logic;
Ch2ResP_o: out std_logic;
Ch2ResN_o: out std_logic;
TriggerP_i: in std_logic;
TriggerN_i: in std_logic;
-- AD9512 SPI
SpiAd9512Sclk_o: out std_logic;
SpiAd9512Mosi_o: out std_logic;
SpiAd9512Miso_i: in std_logic;
SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Ad9512Func_o: out std_logic;
-- clock selection pin of SY58017U
Clk2Sel_o: out std_logic;
-- clock output
ClkOutP_ok: out std_logic;
ClkOutN_ok: out std_logic;
-- temperature chip interface
Onewire_io: inout std_logic;
-- LEDs
Led_ob: out std_logic_vector(4 downto 1)
);
end entity;
architecture sp6 of FfpgCoreWrapper is
-- for differential inputs
signal ClkIn0_k, Trigger: std_logic;
-- for differentials outputs
signal Ch1Set, Ch1Res, Ch2Set, Ch2Res: std_logic;
signal ClkOutDdr, ClkOut_k: std_logic;
begin
cClkIn0Ibufgds: IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => ClkIn0P_ik,
IB => ClkIn0N_ik,
O => ClkIn0_k
);
cTriggerIbufds: IBUFDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => TriggerP_i,
IB => TriggerN_i,
O => Trigger
);
cFfpgCore: entity work.FfpgCore(syn)
generic map (
g_ClkFrequency => g_ClkFrequency, -- input clock frequency in Hz
g_Version => g_Version
)
port map (
-- Wishbone connection
Clk_ik => Clk_ik,
Reset_ira => Reset_ira, -- synchronized locally for better timing
Wb_i => Wb_i,
Wb_o => Wb_o,
---- FMC interface
-- clock
ClkIn0_ik => ClkIn0_k,
-- DACs
TriggerDac_o => TriggerDac_o,
VcxoDac_o => VcxoDac_o,
-- output enable
Ch1OutputEnable_o => Ch1OutputEnable_o,
Ch2OutputEnable_o => Ch2OutputEnable_o,
-- delay configuration
DelayValue_ob => DelayValue_ob,
Ch1SetLe_on => Ch1SetLe_on,
Ch1ResLe_on => Ch1ResLe_on,
Ch2SetLe_on => Ch2SetLe_on,
Ch2ResLe_on => Ch2ResLe_on,
Ch1Set_o => Ch1Set,
Ch1Res_o => Ch1Res,
Ch2Set_o => Ch2Set,
Ch2Res_o => Ch2Res,
Trigger_i => Trigger,
-- AD9512 SPI
SpiAd9512Sclk_o => SpiAd9512Sclk_o,
SpiAd9512Mosi_o => SpiAd9512Mosi_o,
SpiAd9512Miso_i => SpiAd9512Miso_i,
SpiAd9512Cs_on => SpiAd9512Cs_on,
-- AD9512 func. pin
Ad9512Func_o => Ad9512Func_o,
-- clock selection pin of SY58017U
Clk2Sel_o => Clk2Sel_o,
-- clock output
ClkOut_ok => ClkOut_k,
-- temperature chip interface
Onewire_io => Onewire_io,
-- LEDs
Led_ob => Led_ob
);
cCh1SetObufds: OBUFDS
port map (
I => Ch1Set,
O => Ch1SetP_o,
OB => Ch1SetN_o
);
cCh1ResObufds: OBUFDS
port map (
I => Ch1Res,
O => Ch1ResP_o,
OB => Ch1ResN_o
);
cCh2SetObufds: OBUFDS
port map (
I => Ch2Set,
O => Ch2SetP_o,
OB => Ch2SetN_o
);
cCh2ResObufds: OBUFDS
port map (
I => Ch2Res,
O => Ch2ResP_o,
OB => Ch2ResN_o
);
cClkOutOddr: ODDR2
generic map(
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => ClkOutDdr,
C0 => ClkOut_k,
C1 => not ClkOut_k,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0'
);
cClkOutObufds: OBUFDS
port map (
I => ClkOutDdr,
O => ClkOutP_ok,
OB => ClkOutN_ok
);
end architecture;
hdl/ffpg/rtl/FfpgSlave.vhd
View file @ 995c4865
......@@ -47,11 +47,11 @@ use ieee.numeric_std.all;
use work.FfpgPkg.all;
use work.ffpg_wbgen2_pkg.all;
use work.wishbone_pkg.all;
use work.sourceid_svec_top_ffpg_pkg;
entity FfpgSlave is
generic (
g_ClkFrequency: positive -- input clock frequency in Hz
g_ClkFrequency: positive; -- input clock frequency in Hz
g_Version: std_logic_vector(31 downto 0)
);
port (
-- Wishbone connection
......@@ -399,8 +399,8 @@ begin
-- Version information
----------------------------------
WbRegsInput.version_major_i <= "00" & unsigned(sourceid_svec_top_ffpg_pkg.version(31 downto 24));
WbRegsInput.version_minor_i <= "00" & unsigned(sourceid_svec_top_ffpg_pkg.version(23 downto 16));
WbRegsInput.version_revision_i <= unsigned(sourceid_svec_top_ffpg_pkg.version(11 downto 0));
WbRegsInput.version_major_i <= "00" & unsigned(g_Version(31 downto 24));
WbRegsInput.version_minor_i <= "00" & unsigned(g_Version(23 downto 16));
WbRegsInput.version_revision_i <= unsigned(g_Version(11 downto 0));
end architecture;
hdl/ffpg/rtl/Manifest.py
View file @ 995c4865
......@@ -2,6 +2,7 @@ files = [
"ffpg_csr.vhd",
"ffpg_csr_pkg.vhd",
"FfpgCore.vhd",
"FfpgCoreWrapper.vhd",
"FfpgPkg.vhd",
"FfpgSlave.vhd",
"Ad9512Control.vhd",
......
gn4124-core @ f69c9499
Subproject commit f69c9499695d70dcf6ffca9da229defb428713e9
spec @ aee0dc19
Subproject commit aee0dc194d9b86db763acc23d57b55671e6137fd
hdl/syn/common/.gitignore 0 → 100644
View file @ 995c4865
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
*
!.gitignore
!Manifest.py
hdl/syn/common/Manifest.py 0 → 100644
View file @ 995c4865
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
files = [
"sourceid_{}_pkg.vhd".format(syn_top),
]
try:
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': syn_top})
except Exception as e:
print("Error: cannot generate source id file")
raise
hdl/syn/spec/.gitignore 0 → 100644
View file @ 995c4865
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/spec/Manifest.py 0 → 100644
View file @ 995c4865
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
board = "spec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top_ffpg"
syn_project = "spec_top_ffpg.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
"spec_top_ffpg.ucf",
]
# Ideally this should be done by hdlmake itself, to allow downstream Manifests to be able to use the
# fetchto variable independent of where those Manifests reside in the filesystem.
# However, this needs to happen after the files section above, otherwise the two ucf files from the
# dependency will not be taken into account!!!
import os
fetchto = os.path.abspath(fetchto)
modules = {
"local" : [
"../common",
"../../top/spec",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec_base_ucf = ['onewire', 'spi']
ctrls = ["bank3_64b_32b"]
hdl/syn/spec/spec_top_ffpg.ucf 0 → 100644
View file @ 995c4865
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#===============================================================================
# The IO Location Constraints
#===============================================================================
#----------------------------------------
# FMC slot 0
#----------------------------------------
# NET "fmc0_clk0m2c_n" LOC = F16;
# NET "fmc0_clk0m2c_n" IOSTANDARD = "LVDS_25";
# NET "fmc0_clk0m2c_p" LOC = E16;
# NET "fmc0_clk0m2c_p" IOSTANDARD = "LVDS_25";
# NET "fmc0_clk1m2c_n" LOC = L22;
# NET "fmc0_clk1m2c_n" IOSTANDARD = "LVDS_18";
# NET "fmc0_clk1m2c_p" LOC = L20;
# NET "fmc0_clk1m2c_p" IOSTANDARD = "LVDS_18";
# NET "fmc0_dp0c2m_n" LOC = C7;
# NET "fmc0_dp0c2m_p" LOC = D7;
# NET "fmc0_dp0m2c_n" LOC = A6;
# NET "fmc0_dp0m2c_p" LOC = B6;
# NET "fmc0_gbtclk0m2c_n" LOC = B10;
# NET "fmc0_gbtclk0m2c_p" LOC = A10;
NET "Fmc0ClkIn0P_ik" LOC = Y11; # fmc0_la_p[0]
NET "Fmc0ClkIn0P_ik" IOSTANDARD = "LVDS_25";
NET "Fmc0Ch1ResLe_on" LOC = AA12; # fmc0_la_p[1]
NET "Fmc0Ch1ResLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch1SetP_o" LOC = W6; # fmc0_la_p[2]
NET "Fmc0Ch1SetP_o" IOSTANDARD = "LVDS_25";
NET "Fmc0Onewire_io" LOC = V7; # fmc0_la_p[3]
NET "Fmc0Onewire_io" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch1ResP_o" LOC = T8; # fmc0_la_p[4]
NET "Fmc0Ch1ResP_o" IOSTANDARD = "LVDS_25";
# NET "fmc0_la_p[5]" LOC = AA6;
# NET "fmc0_la_p[5]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Led_ob[4]" LOC = Y5; # fmc0_la_p[6]
NET "Fmc0Led_ob[4]" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[7]" LOC = U9;
# NET "fmc0_la_p[7]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch1OutputEnable_o" LOC = R9; # fmc0_la_p[8]
NET "Fmc0Ch1OutputEnable_o" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[9]" LOC = Y7;
# NET "fmc0_la_p[9]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Led_ob[2]" LOC = AA8; # fmc0_la_p[10]
NET "Fmc0Led_ob[2]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2SetP_o" LOC = W10; # fmc0_la_p[11]
NET "Fmc0Ch2SetP_o" IOSTANDARD = "LVDS_25";
NET "Fmc0Ch1OutCal_i" LOC = T10; # fmc0_la_p[12]
NET "Fmc0Ch1OutCal_i" IOSTANDARD = "LVCMOS25";
NET "Fmc0ClkOutP_ok" LOC = Y9; # fmc0_la_p[13]
NET "Fmc0ClkOutP_ok" IOSTANDARD = "LVDS_25";
NET "Fmc0TriggerP_i" LOC = AA4; # fmc0_la_p[14]
NET "Fmc0TriggerP_i" IOSTANDARD = "LVDS_25";
# NET "fmc0_la_p[15]" LOC = V11;
# NET "fmc0_la_p[15]" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[16]" LOC = W12;
# NET "fmc0_la_p[16]" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[17]" LOC = Y13;
# NET "fmc0_la_p[17]" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[18]" LOC = T12;
# NET "fmc0_la_p[18]" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[3]" LOC = Y15; # fmc0_la_p[19]
NET "Fmc0DelayValue_ob[3]" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[2]" LOC = R11; # fmc0_la_p[20]
NET "Fmc0DelayValue_ob[2]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2ResP_o" LOC = V13; # fmc0_la_p[21]
NET "Fmc0Ch2ResP_o" IOSTANDARD = "LVDS_25";
NET "Fmc0Ad9512Func_o" LOC = R13; # fmc0_la_p[22]
NET "Fmc0Ad9512Func_o" IOSTANDARD = "LVCMOS25";
NET "Fmc0TriggerDac_o_SerialClock" LOC = AA16; # fmc0_la_p[23]
NET "Fmc0TriggerDac_o_SerialClock" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[7]" LOC = W14; # fmc0_la_p[24]
NET "Fmc0DelayValue_ob[7]" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[6]" LOC = T15; # fmc0_la_p[25]
NET "Fmc0DelayValue_ob[6]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2ResLe_on" LOC = Y17; # fmc0_la_p[26]
NET "Fmc0Ch2ResLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc0VcxoDac_o_SerialClock" LOC = AA18; # fmc0_la_p[27]
NET "Fmc0VcxoDac_o_SerialClock" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[28]" LOC = Y16;
# NET "fmc0_la_p[28]" IOSTANDARD = "LVCMOS25";
NET "Fmc0SpiAd9512Sclk_o" LOC = W17; # fmc0_la_p[29]
NET "Fmc0SpiAd9512Sclk_o" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[30]" LOC = V17;
# NET "fmc0_la_p[30]" IOSTANDARD = "LVCMOS25";
NET "Fmc0SpiAd9512Miso_i" LOC = D17; # fmc0_la_p[31]
NET "Fmc0SpiAd9512Miso_i" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[32]" LOC = B20;
# NET "fmc0_la_p[32]" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_p[33]" LOC = C19;
# NET "fmc0_la_p[33]" IOSTANDARD = "LVCMOS25";
NET "Fmc0ClkIn0N_ik" LOC = AB11; # fmc0_la_n[0]
NET "Fmc0ClkIn0N_ik" IOSTANDARD = "LVDS_25";
NET "Fmc0Ch1SetLe_on" LOC = AB12; # fmc0_la_n[1]
NET "Fmc0Ch1SetLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch1SetN_o" LOC = Y6; # fmc0_la_n[2]
NET "Fmc0Ch1SetN_o" IOSTANDARD = "LVDS_25";
# NET "fmc0_la_n[3]" LOC = W8;
# NET "fmc0_la_n[3]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch1ResN_o" LOC = U8; # fmc0_la_n[4]
NET "Fmc0Ch1ResN_o" IOSTANDARD = "LVDS_25";
# NET "fmc0_la_n[5]" LOC = AB6;
# NET "fmc0_la_n[5]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Led_ob[3]" LOC = AB5; # fmc0_la_n[6]
NET "Fmc0Led_ob[3]" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_n[7]" LOC = V9;
# NET "fmc0_la_n[7]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2OutputEnable_o" LOC = R8; # fmc0_la_n[8]
NET "Fmc0Ch2OutputEnable_o" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_n[9]" LOC = AB7;
# NET "fmc0_la_n[9]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Led_ob[1]" LOC = AB8; # fmc0_la_n[10]
NET "Fmc0Led_ob[1]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2SetN_o" LOC = Y10; # fmc0_la_n[11]
NET "Fmc0Ch2SetN_o" IOSTANDARD = "LVDS_25";
NET "Fmc0Ch2OutCal_i" LOC = U10; # fmc0_la_n[12]
NET "Fmc0Ch2OutCal_i" IOSTANDARD = "LVCMOS25";
NET "Fmc0ClkOutN_ok" LOC = AB9; # fmc0_la_n[13]
NET "Fmc0ClkOutN_ok" IOSTANDARD = "LVDS_25";
NET "Fmc0TriggerN_i" LOC = AB4; # fmc0_la_n[14]
NET "Fmc0TriggerN_i" IOSTANDARD = "LVDS_25";
NET "Fmc0DelayValue_ob[1]" LOC = W11; # fmc0_la_n[15]
NET "Fmc0DelayValue_ob[1]" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[0]" LOC = Y12; # fmc0_la_n[16]
NET "Fmc0DelayValue_ob[0]" IOSTANDARD = "LVCMOS25";
NET "Fmc0TriggerDac_o_FrameSynchronization_n" LOC = AB13; # fmc0_la_n[17]
NET "Fmc0TriggerDac_o_FrameSynchronization_n" IOSTANDARD = "LVCMOS25";
NET "Fmc0VcxoDac_o_FrameSynchronization_n" LOC = U12; # fmc0_la_n[18]
NET "Fmc0VcxoDac_o_FrameSynchronization_n" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[5]" LOC = AB15; # fmc0_la_n[19]
NET "Fmc0DelayValue_ob[5]" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[4]" LOC = T11; # fmc0_la_n[20]
NET "Fmc0DelayValue_ob[4]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2ResN_o" LOC = W13; # fmc0_la_n[21]
NET "Fmc0Ch2ResN_o" IOSTANDARD = "LVDS_25";
NET "Fmc0Clk2Sel_o" LOC = T14; # fmc0_la_n[22]
NET "Fmc0Clk2Sel_o" IOSTANDARD = "LVCMOS25";
NET "Fmc0TriggerDac_o_SerialData" LOC = AB16; # fmc0_la_n[23]
NET "Fmc0TriggerDac_o_SerialData" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[9]" LOC = Y14; # fmc0_la_n[24]
NET "Fmc0DelayValue_ob[9]" IOSTANDARD = "LVCMOS25";
NET "Fmc0DelayValue_ob[8]" LOC = U15; # fmc0_la_n[25]
NET "Fmc0DelayValue_ob[8]" IOSTANDARD = "LVCMOS25";
NET "Fmc0Ch2SetLe_on" LOC = AB17; # fmc0_la_n[26]
NET "Fmc0Ch2SetLe_on" IOSTANDARD = "LVCMOS25";
NET "Fmc0VcxoDac_o_SerialData" LOC = AB18; # fmc0_la_n[27]
NET "Fmc0VcxoDac_o_SerialData" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_n[28]" LOC = W15;
# NET "fmc0_la_n[28]" IOSTANDARD = "LVCMOS25";
NET "Fmc0SpiAd9512Mosi_o" LOC = Y18; # fmc0_la_n[29]
NET "Fmc0SpiAd9512Mosi_o" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_n[30]" LOC = W18;
# NET "fmc0_la_n[30]" IOSTANDARD = "LVCMOS25";
NET "Fmc0SpiAd9512Cs_on" LOC = C18; # fmc0_la_n[31]
NET "Fmc0SpiAd9512Cs_on" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_n[32]" LOC = A20;
# NET "fmc0_la_n[32]" IOSTANDARD = "LVCMOS25";
# NET "fmc0_la_n[33]" LOC = A19;
# NET "fmc0_la_n[33]" IOSTANDARD = "LVCMOS25";
# NET "fmc0_pg_c2m" LOC = AA14;
# NET "fmc0_pg_c2m" IOSTANDARD = "LVCMOS25";
# NET "fmc0_tck" LOC = G8;
# NET "fmc0_tck" IOSTANDARD = "LVCMOS25";
# NET "fmc0_tdi" LOC = H11;
# NET "fmc0_tdi" IOSTANDARD = "LVCMOS25";
# NET "fmc0_tdo" LOC = F9;
# NET "fmc0_tdo" IOSTANDARD = "LVCMOS25";
# NET "fmc0_tms" LOC = H10;
# NET "fmc0_tms" IOSTANDARD = "LVCMOS25";
# NET "fmc0_trst" LOC = E6;
# NET "fmc0_trst" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints
#===============================================================================
# RF clock
NET "Fmc0ClkIn0P_ik" TNM_NET = tmn_Fmc0ClkIn0P_ik;
TIMESPEC TS_Fmc0ClkIn0P_ik = PERIOD "tmn_Fmc0ClkIn0P_ik" 4.97 ns HIGH 50%;
OFFSET = OUT 2.22 ns AFTER "Fmc0ClkIn0P_ik";
TIMESPEC TS_Fmc0MultiCycle = FROM tmn_Fmc0ClkIn0P_ik TO PADS TS_Fmc0ClkIn0P_ik*3;
#===============================================================================
# False Path
#===============================================================================
# Reset
# add top level resets here? and what about CDC in DelayedPulseGenerator.vhd ?
hdl/syn/spec/syn_extra_steps.tcl 0 → 100644
View file @ 995c4865
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/svec/Manifest.py
View file @ 995c4865
......@@ -20,7 +20,6 @@ if locals().get('fetchto', None) is None:
files = [
"buildinfo_pkg.vhd",
"sourceid_{}_pkg.vhd".format(syn_top),
"svec_top_ffpg.ucf",
]
......@@ -33,17 +32,11 @@ fetchto = os.path.abspath(fetchto)
modules = {
"local" : [
"../common",
"../../top/svec",
],
}
try:
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': syn_top})
except Exception as e:
print("Error: cannot generate source id file")
raise
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
hdl/top/spec/Manifest.py 0 → 100644
View file @ 995c4865
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
files = [
"spec_top_ffpg.vhd",
"spec_top_ffpg_map.vhd",
]
modules = {
"local" : [
"../../ffpg/rtl",
"../../ip_cores/spec",
"../../ip_cores/general-cores",
"../../ip_cores/gn4124-core",
"../../ip_cores/ddr3-sp6-core",
"../../ip_cores/wr-cores",
],
#"git" : [
# "https://ohwr.org/project/spec.git",
# "https://ohwr.org/project/general-cores.git",
# "https://ohwr.org/project/gn4124-core.git",
# "https://ohwr.org/project/ddr3-sp6-core.git",
# "https://ohwr.org/project/wr-cores.git",
#],
}
hdl/top/spec/spec_top_ffpg.vhd 0 → 100644
View file @ 995c4865
This diff is collapsed.
hdl/top/spec/spec_top_ffpg_map.cheby 0 → 100644
View file @ 995c4865
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: spec_top_ffpg_map
bus: wb-32-be
size: 0x80000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ffpg0
description: FFPG core 0
address: 0x20000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/spec/spec_top_ffpg_map.vhd 0 → 100644
View file @ 995c4865
-- Do not edit. Generated by cheby 1.6.dev0 using these options:
-- -i spec_top_ffpg_map.cheby --gen-hdl spec_top_ffpg_map.vhd
-- Generated on Fri Feb 24 17:21:10 2023 by tlevens
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity spec_top_ffpg_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- a ROM containing the carrier metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- FFPG core 0
ffpg0_i : in t_wishbone_master_in;
ffpg0_o : out t_wishbone_master_out
);
end spec_top_ffpg_map;
architecture syn of spec_top_ffpg_map is
signal adr_int : std_logic_vector(18 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal ffpg0_re : std_logic;
signal ffpg0_we : std_logic;
signal ffpg0_wt : std_logic;
signal ffpg0_rt : std_logic;
signal ffpg0_tr : std_logic;
signal ffpg0_wack : std_logic;
signal ffpg0_rack : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(18 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(18 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wr_dat_d0;
-- Interface ffpg0
ffpg0_tr <= ffpg0_wt or ffpg0_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ffpg0_rt <= '0';
ffpg0_wt <= '0';
else
ffpg0_rt <= (ffpg0_rt or ffpg0_re) and not ffpg0_rack;
ffpg0_wt <= (ffpg0_wt or ffpg0_we) and not ffpg0_wack;
end if;
end if;
end process;
ffpg0_o.cyc <= ffpg0_tr;
ffpg0_o.stb <= ffpg0_tr;
ffpg0_wack <= ffpg0_i.ack and ffpg0_wt;
ffpg0_rack <= ffpg0_i.ack and ffpg0_rt;
ffpg0_o.adr <= ((14 downto 0 => '0') & adr_int(16 downto 2)) & (1 downto 0 => '0');
ffpg0_o.sel <= wr_sel_d0;
ffpg0_o.we <= ffpg0_wt;
ffpg0_o.dat <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, metadata_wack, ffpg0_wack) begin
metadata_we <= '0';
ffpg0_we <= '0';
case wr_adr_d0(18 downto 17) is
when "00" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_int <= metadata_wack;
when "01" =>
-- Submap ffpg0
ffpg0_we <= wr_req_d0;
wr_ack_int <= ffpg0_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (adr_int, rd_req_int, metadata_i.dat, metadata_rack, ffpg0_i.dat,
ffpg0_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
ffpg0_re <= '0';
case adr_int(18 downto 17) is
when "00" =>
-- Submap metadata
metadata_re <= rd_req_int;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "01" =>
-- Submap ffpg0
ffpg0_re <= rd_req_int;
rd_dat_d0 <= ffpg0_i.dat;
rd_ack_d0 <= ffpg0_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/top/svec/Manifest.py
View file @ 995c4865
......@@ -20,5 +20,7 @@ modules = {
# "https://ohwr.org/project/svec.git",
# "https://ohwr.org/project/general-cores.git",
# "https://ohwr.org/project/vme64x-core.git",
# "https://ohwr.org/project/ddr3-sp6-core.git",
# "https://ohwr.org/project/wr-cores.git",
#],
}
hdl/top/svec/svec_top_ffpg.vhd
View file @ 995c4865
This diff is collapsed.
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