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FMC DEL 1ns 2cha
Commits
544ee006
Commit
544ee006
authored
Aug 18, 2016
by
Jan Pospisil
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added reset to LOAD_EXT register in WbSlaveWrapper
parent
5e21ea7c
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87 additions
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60 deletions
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-60
WbSlaveWrapper.vhd
hdl/ffpg/rtl/WbSlaveWrapper.vhd
+87
-60
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hdl/ffpg/rtl/WbSlaveWrapper.vhd
View file @
544ee006
...
@@ -104,67 +104,94 @@ begin
...
@@ -104,67 +104,94 @@ begin
-- local registers for LOAD_EXT fields
-- local registers for LOAD_EXT fields
pLocalRegs
:
process
(
Clk_ik
)
is
begin
pLocalRegs
:
process
(
Clk_ik
)
is
begin
if
rising_edge
(
Clk_ik
)
then
if
rising_edge
(
Clk_ik
)
then
-- TODO: reset?
if
Reset_ir
=
'1'
then
control_clock_selection_load
<=
'0'
;
control_clock_selection_load
<=
'0'
;
control_ch1_mode_load
<=
'0'
;
control_ch1_mode_load
<=
'0'
;
control_ch2_mode_load
<=
'0'
;
control_ch2_mode_load
<=
'0'
;
vcxo_voltage_load
<=
'0'
;
vcxo_voltage_load
<=
'0'
;
clock_divider_hi_load
<=
'0'
;
clock_divider_hi_load
<=
'0'
;
ch1_delay_set_load
<=
'0'
;
ch1_delay_set_load
<=
'0'
;
ch1_delay_reset_load
<=
'0'
;
ch1_delay_reset_load
<=
'0'
;
ch2_delay_set_load
<=
'0'
;
ch2_delay_set_load
<=
'0'
;
ch2_delay_reset_load
<=
'0'
;
ch2_delay_reset_load
<=
'0'
;
trigger_threshold_load
<=
'0'
;
trigger_threshold_load
<=
'0'
;
overflow_load
<=
'0'
;
overflow_load
<=
'0'
;
trigger_latency_load
<=
'0'
;
trigger_latency_load
<=
'0'
;
if
WbRegsOutput
.
control_clock_selection_load_o
=
'1'
then
control_clock_selection
<=
(
others
=>
'0'
);
control_clock_selection
<=
WbRegsOutput
.
control_clock_selection_o
;
control_ch1_mode
<=
(
others
=>
'0'
);
control_clock_selection_load
<=
'1'
;
control_ch2_mode
<=
(
others
=>
'0'
);
end
if
;
vcxo_voltage
<=
(
others
=>
'0'
);
if
WbRegsOutput
.
control_ch1_mode_load_o
=
'1'
then
clock_divider_hi
<=
(
others
=>
'0'
);
control_ch1_mode
<=
WbRegsOutput
.
control_ch1_mode_o
;
ch1_delay_set
<=
(
others
=>
'0'
);
control_ch1_mode_load
<=
'1'
;
ch1_delay_reset
<=
(
others
=>
'0'
);
end
if
;
ch2_delay_set
<=
(
others
=>
'0'
);
if
WbRegsOutput
.
control_ch2_mode_load_o
=
'1'
then
ch2_delay_reset
<=
(
others
=>
'0'
);
control_ch2_mode
<=
WbRegsOutput
.
control_ch2_mode_o
;
trigger_threshold
<=
(
others
=>
'0'
);
control_ch2_mode_load
<=
'1'
;
overflow
<=
(
others
=>
'0'
);
end
if
;
trigger_latency
<=
(
others
=>
'0'
);
if
WbRegsOutput
.
vcxo_voltage_load_o
=
'1'
then
else
vcxo_voltage
<=
WbRegsOutput
.
vcxo_voltage_o
;
control_clock_selection_load
<=
'0'
;
vcxo_voltage_load
<=
'1'
;
control_ch1_mode_load
<=
'0'
;
end
if
;
control_ch2_mode_load
<=
'0'
;
if
WbRegsOutput
.
clock_divider_hi_load_o
=
'1'
then
vcxo_voltage_load
<=
'0'
;
clock_divider_hi
<=
WbRegsOutput
.
clock_divider_hi_o
;
clock_divider_hi_load
<=
'0'
;
clock_divider_hi_load
<=
'1'
;
ch1_delay_set_load
<=
'0'
;
end
if
;
ch1_delay_reset_load
<=
'0'
;
if
WbRegsOutput
.
ch1_delay_set_load_o
=
'1'
then
ch2_delay_set_load
<=
'0'
;
ch1_delay_set
<=
WbRegsOutput
.
ch1_delay_set_o
;
ch2_delay_reset_load
<=
'0'
;
ch1_delay_set_load
<=
'1'
;
trigger_threshold_load
<=
'0'
;
end
if
;
overflow_load
<=
'0'
;
if
WbRegsOutput
.
ch1_delay_reset_load_o
=
'1'
then
trigger_latency_load
<=
'0'
;
ch1_delay_reset
<=
WbRegsOutput
.
ch1_delay_reset_o
;
ch1_delay_reset_load
<=
'1'
;
if
WbRegsOutput
.
control_clock_selection_load_o
=
'1'
then
end
if
;
control_clock_selection
<=
WbRegsOutput
.
control_clock_selection_o
;
if
WbRegsOutput
.
ch2_delay_set_load_o
=
'1'
then
control_clock_selection_load
<=
'1'
;
ch2_delay_set
<=
WbRegsOutput
.
ch2_delay_set_o
;
end
if
;
ch2_delay_set_load
<=
'1'
;
if
WbRegsOutput
.
control_ch1_mode_load_o
=
'1'
then
end
if
;
control_ch1_mode
<=
WbRegsOutput
.
control_ch1_mode_o
;
if
WbRegsOutput
.
ch2_delay_reset_load_o
=
'1'
then
control_ch1_mode_load
<=
'1'
;
ch2_delay_reset
<=
WbRegsOutput
.
ch2_delay_reset_o
;
end
if
;
ch2_delay_reset_load
<=
'1'
;
if
WbRegsOutput
.
control_ch2_mode_load_o
=
'1'
then
end
if
;
control_ch2_mode
<=
WbRegsOutput
.
control_ch2_mode_o
;
if
WbRegsOutput
.
trigger_threshold_load_o
=
'1'
then
control_ch2_mode_load
<=
'1'
;
trigger_threshold
<=
WbRegsOutput
.
trigger_threshold_o
;
end
if
;
trigger_threshold_load
<=
'1'
;
if
WbRegsOutput
.
vcxo_voltage_load_o
=
'1'
then
end
if
;
vcxo_voltage
<=
WbRegsOutput
.
vcxo_voltage_o
;
if
WbRegsOutput
.
overflow_load_o
=
'1'
then
vcxo_voltage_load
<=
'1'
;
overflow
<=
WbRegsOutput
.
overflow_o
;
end
if
;
overflow_load
<=
'1'
;
if
WbRegsOutput
.
clock_divider_hi_load_o
=
'1'
then
end
if
;
clock_divider_hi
<=
WbRegsOutput
.
clock_divider_hi_o
;
if
WbRegsOutput
.
trigger_latency_load_o
=
'1'
then
clock_divider_hi_load
<=
'1'
;
trigger_latency
<=
WbRegsOutput
.
trigger_latency_o
;
end
if
;
trigger_latency_load
<=
'1'
;
if
WbRegsOutput
.
ch1_delay_set_load_o
=
'1'
then
ch1_delay_set
<=
WbRegsOutput
.
ch1_delay_set_o
;
ch1_delay_set_load
<=
'1'
;
end
if
;
if
WbRegsOutput
.
ch1_delay_reset_load_o
=
'1'
then
ch1_delay_reset
<=
WbRegsOutput
.
ch1_delay_reset_o
;
ch1_delay_reset_load
<=
'1'
;
end
if
;
if
WbRegsOutput
.
ch2_delay_set_load_o
=
'1'
then
ch2_delay_set
<=
WbRegsOutput
.
ch2_delay_set_o
;
ch2_delay_set_load
<=
'1'
;
end
if
;
if
WbRegsOutput
.
ch2_delay_reset_load_o
=
'1'
then
ch2_delay_reset
<=
WbRegsOutput
.
ch2_delay_reset_o
;
ch2_delay_reset_load
<=
'1'
;
end
if
;
if
WbRegsOutput
.
trigger_threshold_load_o
=
'1'
then
trigger_threshold
<=
WbRegsOutput
.
trigger_threshold_o
;
trigger_threshold_load
<=
'1'
;
end
if
;
if
WbRegsOutput
.
overflow_load_o
=
'1'
then
overflow
<=
WbRegsOutput
.
overflow_o
;
overflow_load
<=
'1'
;
end
if
;
if
WbRegsOutput
.
trigger_latency_load_o
=
'1'
then
trigger_latency
<=
WbRegsOutput
.
trigger_latency_o
;
trigger_latency_load
<=
'1'
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
end
process
;
...
...
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