The FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC card in FMC (FPGA Mezzanine Card) format. By default it uses only signals from the LPC rows of the HPC connector that is mounted. The gain can be set by software in three steps: +/-50mV, +/-0.5V, +/-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of +/-5V that is independent on the chosen gain range.
max. sample rate
105 MSPS (default 100MSPS)
30 MHz. DC-coupled (40 MHz possible by changing eight capacitors)
original specification: 11.0, 11.5, 11.7 bit (@ /-50mV,/-0.5V, +/-5V range) see below for actual 2017 measurements
original specification: 67.7 dB, 70.8 dB, 72.2 dB (@ /-50mV,/-0.5V, +/-5V range) see below for actual 2017 measurements