Programming languages used in this repository

  •   VHDL
    50.47 %
  •   C
    31.71 %
  •   SystemVerilog
    8.05 %
  •   Stata
    3.07 %
  •   Verilog
    2.52 %
  •   Makefile
    1.87 %
  •   Python
    1.3 %
  •   Tcl
    1.0 %

Commit statistics for master Nov 23 - Jun 11

  • Total: 1358 commits
  • Average per day: 0.3 commits
  • Authors: 21

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