Programming languages used in this repository

  •   Verilog
    77.99 %
  •   VHDL
    10.48 %
  •   HTML
    4.53 %
  •   SystemVerilog
    2.37 %
  •   C
    1.61 %
  •   Makefile
    1.46 %
  •   Stata
    1.12 %
  •   Tcl
    0.21 %
  •   Shell
    0.07 %
  •   Python
    0.07 %
  •   Coq
    0.06 %
  •   Batchfile
    0.04 %

Commit statistics for master Nov 23 - Apr 25

  • Total: 284 commits
  • Average per day: 0.2 commits
  • Authors: 8

Commits per day of month

Commits per weekday

Commits per day hour (UTC)