Programming languages used in this repository

  •   VHDL
    50.59 %
  •   C
    31.95 %
  •   SystemVerilog
    7.86 %
  •   Stata
    3.0 %
  •   Verilog
    2.47 %
  •   Makefile
    1.89 %
  •   Python
    1.27 %
  •   Tcl
    0.98 %

Commit statistics for master Nov 23 - Sep 10

  • Total: 1452 commits
  • Average per day: 0.3 commits
  • Authors: 22

Commits per day of month

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Commits per day hour (UTC)