Programming languages used in this repository

  •   VHDL
    38.88 %
  •   Verilog
    25.86 %
  •   SystemVerilog
    14.86 %
  •   C
    10.67 %
  •   Stata
    8.21 %
  •   Coq
    0.57 %
  •   Python
    0.39 %
  •   Makefile
    0.34 %
  •   Tcl
    0.23 %

Commit statistics for master Nov 23 - Sep 22

  • Total: 1242 commits
  • Average per day: 0.3 commits
  • Authors: 21

Commits per day of month

Commits per weekday

Commits per day hour (UTC)