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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).
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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
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Mathieu Saccani / VME64x core - msaccani
GNU Lesser General Public License v2.1 onlyA VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated -
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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A simple VME64x carrier for two low pin count FPGA Mezzanine Cards (VITA 57). It has memory and clocking resources and supports the White Rabbit timing and control network. Commercially available. More info at the Wiki page
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An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page
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FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page
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This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification
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The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page
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Gateware (HDL design) for FMC TDC 1ns 5cha on SPEC and SVEC carriers.
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Gateware (HDL design) for FMC ADC 100M 14b 4cha on SPEC and SVEC carriers.
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
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DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.
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A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page
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A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.
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Projects / VME64x core
GNU Lesser General Public License v2.1 onlyA VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated -