R
Resource Evaluation of WR switch HDL for Ultrascale Plus
The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
Project ID: 11185
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Marek Gumiński authoredacb702fb
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| doc | ||
| ip_cores | ||
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| platform | ||
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| syn | ||
| testbench | ||
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| .gitignore | ||
| .gitmodules | ||
| Manifest.py | ||
| README | ||
| README.md |