U
urv-core
The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
Project ID: 10895
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Tristan Gingold authored
Release v1.1 See merge request be-cem-edl/common/urv-core!1
65e80de2
| Name |
Last commit
|
Last update |
|---|---|---|
| ip_cores | ||
| rtl | ||
| sw | ||
| syn/spec | ||
| tb | ||
| top/spec | ||
| .gitmodules | ||
| Manifest.py |