Avoid use of phony targets (like tools): be explicit

There's a bug on the PCB, the ext clock buffer enable is tied to EXT PLL (AD9516) reset, but the polarities differ. We don't need this PLL chip as the eRTM15 10M input offers superior timing performance. We just need the input buffer and the clk_10m_ext going to the FPGA for various calibration purposes.

tools/wrpc: move SPLL debug recorder to the Swiss Rabbit Knife (R) tool, also works now on platforms other than the eRTM

so that ppsi is built directly by the wrc Makefile
(and not using a recursive make)

Fixes some format warning
(stdint.h now comes from include/std)

tools: initial version of the SPLL debug trace recorder tool. Currently only the eRTM board is supported

- clean up debug definitions in spll_debug.h
- proper support for AUX channels and events (lock, unlock, gain switch)
- support for up to 8 channels and 16 traces per channel
- optional undersampling for slow readout interfaces (e.g. the UART of the eRTM board)