ertm14: enable CLK_EXT buffer on the ertm14 board

There's a bug on the PCB, the ext clock buffer enable is tied to EXT PLL (AD9516) reset, but the polarities differ. We don't need this PLL chip as the eRTM15 10M input offers superior timing performance. We just need the input buffer and the clk_10m_ext going to the FPGA for various calibration purposes.

ertm14: enable CLK_EXT buffer on the ertm14 board
There's a bug on the PCB, the ext clock buffer enable is tied to EXT PLL (AD9516) reset, but the polarities differ. We don't need this PLL chip as the eRTM15 10M input offers superior timing performance. We just need the input buffer and the clk_10m_ext going to the FPGA for various calibration purposes.
ff1f7f01 · Tomasz Wlostowski · 1130dd83 · ff1f7f01
Commit ff1f7f01 authored May 10, 2023 by Tomasz Wlostowski
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board.c boards/ertm14/board.c +4 -2

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--- a/boards/ertm14/board.c
+++ b/boards/ertm14/board.c
@@ -611,6 +611,7 @@ static void ertm14_spll_setup(void)

    // Aux clock 0 is used for 'factory' calibration of CLKAB/LO/REF outputs.
    spll_set_aux_mode( 0, SPLL_AUX_MODE_PHASE_MONITOR );
+    gen_gpio_out( &pin_tm_clk_aux0_lock_en, 1 );
 }


@@ -2005,6 +2006,9 @@ int ertm14_init_ref_clock_distribution(void)
        ad951x_configure(&board.ad9516_main, &pll_main_ocxo_config);
        // ad951x_configure(&board.ad9516_ext, &pll_ext_10mhz_config);
    }
+
+    gen_gpio_out( &pin_pll_ext_reset, 0 );
+
    return 0;
 }

@@ -3013,8 +3017,6 @@ void ertm14_sync_pulse_cal(void)
        clkab_enable_sync( ertm14_current_state, ERTM14_OUT_CLKB, i, 1 );
    }

-    gen_gpio_out( &pin_tm_clk_aux0_lock_en, 1 );
-
    spll_init( SPLL_MODE_FREE_RUNNING_MASTER, 0, 0 );

    int quit = 0;