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Tomasz Wlostowski authored
There's a bug on the PCB, the ext clock buffer enable is tied to EXT PLL (AD9516) reset, but the polarities differ. We don't need this PLL chip as the eRTM15 10M input offers superior timing performance. We just need the input buffer and the clk_10m_ext going to the FPGA for various calibration purposes.
ff1f7f01
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system_checks.c | ||
wrc_main.c | ||
wrc_main_sim.c |