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Software for White Rabbit PTP Core
Commit 9e51f2e6 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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softpll: overhaul of the debug queue infrastructure: 

- clean up debug definitions in spll_debug.h
- proper support for AUX channels and events (lock, unlock, gain switch)
- support for up to 8 channels and 16 traces per channel
- optional undersampling for slow readout interfaces (e.g. the UART of the eRTM board)
parent 9af14f03
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Showing with 110 additions and 62 deletions
softpll/softpll_ng.c
View file @ 9e51f2e6
......@@ -557,7 +557,7 @@ void spll_show_stats(void)
if (softpll.mode > 0)
pp_printf("softpll: irqs:%d seq:%s mode:%d "
"alignment_state:%d HL%d ML%d HY=%d MY=%d DelCnt=%d setpoint:%d\n",
s->irq_count, statename,
s->irq_count, statename,
s->mode, s->ext.align_state,
s->helper.ld.locked, s->mpll.locked,
s->helper.pi.y, s->mpll.pi.y,
......@@ -654,7 +654,7 @@ static int spll_update_aux_clocks(void)
pll_verbose("softpll: enabled slave aux channel %d\n", ch);
if( !spll_start_channel(ch) )
{
s->seq_state = AUX_LOCK_PLL;
s->seq_state = AUX_LOCK_PLL;
}
done_sth++;
}
......@@ -782,7 +782,7 @@ void spll_set_dac(int index, int value)
SPLL->DAC_HPLL = value;
} else {
SPLL->DAC_MAIN =
SPLL_DAC_MAIN_DAC_SEL_W(index) | (value & 0xffff);
SPLL_DAC_MAIN_DAC_SEL_W(index) | (value & 0xffff);
if (index == 0)
softpll.mpll.pi.y = value;
......@@ -847,38 +847,62 @@ void spll_set_gain_schedule( spll_gain_schedule_t* sch )
enable_irq();
}
void spll_debug_queue_purge(void)
static struct spll_debug_queue_state
{
int dummy;
int undersample_ratio;
uint8_t undersample_count[SPLL_DBG_MAX_SOURCES];
uint8_t undersample_pass[SPLL_DBG_MAX_SOURCES];
int coalesce_threshold;
} dbg_state;
void spll_debug_queue_configure( int undersample, int coalsesce_threshold )
{
int dummy, i;
while (!(SPLL->DFR_HOST_CSR & SPLL_DFR_HOST_CSR_EMPTY))
{
dummy = SPLL->DFR_HOST_R0;
(void) dummy;
}
dbg_state.undersample_ratio = undersample;
dbg_state.coalesce_threshold = coalsesce_threshold * undersample;
for(i=0;i<SPLL_DBG_MAX_SOURCES;i++)
{
dbg_state.undersample_count[i] = 0;
dbg_state.undersample_pass[i] = 0;
}
}
int spll_get_debug_queue_samples( uint32_t *buf, int *count, int undersample )
int spll_get_debug_queue_samples( uint32_t *buf, int *count )
{
int cnt = *count;
int pass = 1;
int und_cnt = 0;
int n_ents = 0;
int full = SPLL->DFR_HOST_CSR & SPLL_DFR_HOST_CSR_FULL;
int latch_full = SPLL->DFR_HOST_CSR & SPLL_DFR_HOST_CSR_FULL;
int latch_count = SPLL_DFR_HOST_CSR_USEDW_R(SPLL->DFR_HOST_CSR);
struct spll_debug_queue_state *st = &dbg_state;
if ( SPLL->DFR_HOST_CSR & SPLL_DFR_HOST_CSR_EMPTY )
if( !latch_full && latch_count < dbg_state.coalesce_threshold )
{
*count = 0;
return 0;
}
while(cnt > 0)
while(1)
{
uint32_t v = SPLL->DFR_HOST_R0;
if ( SPLL->DFR_HOST_CSR & SPLL_DFR_HOST_CSR_EMPTY )
break;
if( n_ents == *count )
break;
uint32_t h = v >> 24;
volatile uint32_t v = SPLL->DFR_HOST_R0;
int signal = SPLL_DBG_EXTRACT_SIGNAL( v );
int src = SPLL_DBG_EXTRACT_SOURCE( v );
if(pass || (h & DBG_EVENT) )
if(st->undersample_pass[src] || signal == SPLL_DBG_SIGNAL_EVENT )
{
*buf++ = v;
n_ents ++;
......@@ -886,14 +910,13 @@ int spll_get_debug_queue_samples( uint32_t *buf, int *count, int undersample )
if( v & 0x80000000 ) // last entry in the record
{
und_cnt++;
if (und_cnt == undersample)
st->undersample_count[src]++;
if (st->undersample_count[src] >= st->undersample_ratio)
{
und_cnt = 0;
pass = 1;
cnt--;
st->undersample_count[src] = 0;
st->undersample_pass[src] = 1;
} else {
pass = 0;
st->undersample_pass[src] = 0;
}
}
......@@ -901,7 +924,7 @@ int spll_get_debug_queue_samples( uint32_t *buf, int *count, int undersample )
*count = n_ents;
if( full )
if( latch_full )
return -ENOSPC;
return 0;
......
softpll/softpll_ng.h
View file @ 9e51f2e6
......@@ -128,8 +128,8 @@ void spll_set_gain_schedule( spll_gain_schedule_t* sch );
int spll_measure_frequency(int osc);
void spll_set_ptracker_average_samples(int channel, int nsamples);
int spll_get_debug_queue_samples( uint32_t *buf, int *count, int undersample );
void spll_debug_queue_purge(void);
int spll_get_debug_queue_samples( uint32_t *buf, int *count );
void spll_debug_queue_configure( int undersample, int coalsesce_threshold );
void spll_set_aux_mode( int channel, int mode );
void spll_set_aux_frequency_ratio( int channel, int div_ref, int div_fb );
......
softpll/spll_common.c
View file @ 9e51f2e6
......@@ -148,8 +148,8 @@ void spll_enable_tagger(int channel, int enable)
pll_verbose("%s: ch %d, OCER 0x%x, RCER 0x%x\n", __FUNCTION__, channel, SPLL->OCER, SPLL->RCER);
}
void spll_debug(int what, int value, int last)
void spll_debug(int src, int what, int value, int last)
{
SPLL->DFR_SPLL =
(last ? 0x80000000 : 0) | (value & 0xffffff) | (what << 24);
(last ? 0x80000000 : 0) | (value & 0xffffff) | (src << 28) | (what << 24);
}
softpll/spll_debug.h
View file @ 9e51f2e6
......@@ -18,22 +18,38 @@ integral/proportional gains on the response of the system.
*/
#define DBG_Y 0
#define DBG_ERR 1
#define DBG_TAG 2
#define DBG_REF 5
#define DBG_PERIOD 3
#define DBG_SAMPLE_ID 6
#ifndef __SPLL_DEBUG_H
#define __SPLL_DEBUG_H
#define DBG_EVENT 0x40
#define DBG_HELPER (6 << 3) /* Sample source: Helper PLL */
#define DBG_EXT (7 << 3) /* Sample source: External Reference PLL */
#define DBG_MAIN(ch) ((ch) << 3) /* ... : Main PLL (or aux) */
#define SPLL_DBG_SIGNAL_Y 0
#define SPLL_DBG_SIGNAL_ERR 1
#define SPLL_DBG_SIGNAL_TAG 2
#define SPLL_DBG_SIGNAL_REF 3
#define SPLL_DBG_SIGNAL_PERIOD 4
#define SPLL_DBG_SIGNAL_SAMPLE_ID 5
#define SPLL_DBG_SIGNAL_EVENT 6
#define SPLL_DBG_SIGNAL_TIME_MS 7
#define SPLL_DBG_SIGNAL_PHASE_CURRENT 8
#define SPLL_DBG_SIGNAL_PHASE_TARGET 9
#define DBG_EVT_START 1 /* PLL has just started */
#define DBG_EVT_LOCKED 2 /* PLL has just become locked */
#define DBG_EVT_GAIN_SWITCH 3 /* PLL switched the PI gain (scheduling) */
#define SPLL_DBG_MAX_SOURCES 8 // maximum number of "source" PLLs
#define SPLL_DBG_SRC_HELPER 0
#define SPLL_DBG_SRC_MAIN 1
#define SPLL_DBG_SRC_EXT 2
#define SPLL_DBG_SRC_AUX(n) (3 + ((n)&0x3)) /* ... : Main PLL aux clock N */
#define SPLL_DBG_LAST_FLAG 0x80
#define SPLL_DBG_EVT_START 1 /* PLL has just started */
#define SPLL_DBG_EVT_LOCK_ACQUIRED 2 /* PLL has just become locked */
#define SPLL_DBG_EVT_GAIN_SWITCH 3 /* PLL switched the PI gain (scheduling) */
#define SPLL_DBG_EVT_LOCK_LOSS 4 /* PLL has just lost lock */
#define SPLL_DBG_EXTRACT_SOURCE(x) ( (x >> 28) & 0x7 )
#define SPLL_DBG_EXTRACT_SIGNAL(x) ( (x >> 24) & 0xf )
#define SPLL_DBG_EXTRACT_VALUE(x) (x & 0xffffff)
#define SPLL_DBG_IS_LAST_RECORD(x) ( x&0x80000000 )
/* Writes a parameter to the debug FIFO.
......@@ -45,4 +61,8 @@ what: type of the parameter and its' source. For example,
last: when non-zero, indicates the last parameter in a sample.
*/
void spll_debug(int what, int value, int last);
void spll_debug(int src, int what, int value, int last);
#endif
softpll/spll_external.c
View file @ 9e51f2e6
......@@ -47,7 +47,8 @@ void external_start(struct spll_external_state *s)
s->align_state = ALIGN_STATE_WAIT_CLKIN;
s->enabled = 1;
spll_debug (DBG_EVENT | DBG_EXT, DBG_EVT_START, 1);
spll_debug ( SPLL_DBG_SRC_EXT, SPLL_DBG_SIGNAL_EVENT, SPLL_DBG_EVT_START, 1 );
}
int external_locked(volatile struct spll_external_state *s)
......
softpll/spll_helper.c
View file @ 9e51f2e6
......@@ -40,8 +40,8 @@ int helper_update(struct spll_helper_state *s, int tag,
int err, y;
if (source == s->ref_src) {
spll_debug(DBG_TAG | DBG_HELPER, tag, 0);
spll_debug(DBG_REF | DBG_HELPER, s->p_setpoint, 0);
spll_debug(SPLL_DBG_SRC_HELPER, SPLL_DBG_SIGNAL_TAG, tag, 0);
spll_debug(SPLL_DBG_SRC_HELPER, SPLL_DBG_SIGNAL_REF, s->p_setpoint, 0);
if (s->tag_d0 < 0) {
s->p_setpoint = tag;
......@@ -75,9 +75,10 @@ int helper_update(struct spll_helper_state *s, int tag,
y = pi_update((spll_pi_t *)&s->pi, err);
SPLL->DAC_HPLL = y;
spll_debug(DBG_SAMPLE_ID | DBG_HELPER, s->sample_n++, 0);
spll_debug(DBG_Y | DBG_HELPER, y, 0);
spll_debug(DBG_ERR | DBG_HELPER, err, 1);
spll_debug(SPLL_DBG_SRC_HELPER, SPLL_DBG_SIGNAL_TIME_MS, timer_get_tics(), 0);
spll_debug(SPLL_DBG_SRC_HELPER, SPLL_DBG_SIGNAL_SAMPLE_ID, s->sample_n++, 0);
spll_debug(SPLL_DBG_SRC_HELPER, SPLL_DBG_SIGNAL_Y, y, 0);
spll_debug(SPLL_DBG_SRC_HELPER, SPLL_DBG_SIGNAL_ERR, err, 1);
if (ld_update((spll_lock_det_t *)&s->ld, err))
return SPLL_LOCKED;
......@@ -103,7 +104,7 @@ void helper_start(struct spll_helper_state *s)
ld_init((spll_lock_det_t *)&s->ld);
spll_enable_tagger(s->ref_src, 1);
spll_debug(DBG_EVENT | DBG_HELPER, DBG_EVT_START, 1);
spll_debug(SPLL_DBG_SRC_HELPER, SPLL_DBG_SIGNAL_EVENT, SPLL_DBG_EVT_START, 1);
}
void helper_switch_reference(struct spll_helper_state *s, int new_ref)
......
softpll/spll_main.c
View file @ 9e51f2e6
......@@ -56,6 +56,7 @@ void mpll_init(struct spll_main_state *s, int id_ref, int id_out)
s->id_ref = id_ref;
s->id_out = id_out;
s->dac_index = id_out - spll_n_chan_ref;
s->dbg_src_id = (s->dac_index == 0) ? SPLL_DBG_SRC_MAIN : SPLL_DBG_SRC_AUX( s->dac_index - 1 );
#ifdef CONFIG_FRAC_SPLL
s->div_ref = s->div_fb = 0;
s->frequency_lock_threshold = 1000;
......@@ -89,7 +90,7 @@ static inline void mpll_handle_gain_schedule( struct spll_main_state *s )
}
else if ( !s->gain_sched->locked_d && s->ld.locked ) // PLL lock acquired? advance stage
{
//spll_debug(DBG_EVENT | DBG_MAIN, DBG_EVT_GAIN_SWITCH, 0);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_EVENT, SPLL_DBG_EVT_GAIN_SWITCH, 0);
if ( s->gain_sched->current_stage == s->gain_sched->n_stages - 1 )
{
s->locked = 1;
......@@ -132,6 +133,7 @@ void mpll_start(struct spll_main_state *s)
s->tag_out = -1;
s->tag_ref_d = -1;
s->tag_out_d = -1;
s->phase_shift_target = 0;
s->phase_shift_current = 0;
s->sample_n = 0;
......@@ -162,7 +164,7 @@ void mpll_start(struct spll_main_state *s)
spll_enable_tagger(s->id_ref, 1);
spll_enable_tagger(s->id_out, 1);
spll_debug(DBG_EVENT | DBG_MAIN(s->id_out - spll_n_chan_ref), DBG_EVT_START, 1);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_EVENT, SPLL_DBG_EVT_START, 1);
}
void mpll_stop(struct spll_main_state *s)
......@@ -197,7 +199,7 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
if (source == s->id_ref)
{
s->tag_ref = tag;
#ifdef CONFIG_FRAC_SPLL
s->n_ref++;
......@@ -217,7 +219,7 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
s->tag_out_raw = tag;
if (s->div_ref == 0)
{
s->tag_out = tag;
s->tag_out = tag;
s->n_out++;
}
else
......@@ -302,7 +304,7 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
else
#endif
{
err = s->adder_ref + s->tag_ref - s->adder_out - s->tag_out;
err = s->adder_ref + s->tag_ref - s->adder_out - s->tag_out;
}
#ifndef WITH_SEQUENCING
......@@ -325,7 +327,7 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
#endif
y = pi_update((spll_pi_t *)&s->pi, err);
if(!s->vco_freeze )
if(!s->vco_freeze)
{
SPLL->DAC_MAIN = SPLL_DAC_MAIN_VALUE_W(y)
| SPLL_DAC_MAIN_DAC_SEL_W(s->dac_index);
......@@ -333,14 +335,14 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
if (s->dac_index == 0)
spll_log_dac(y);
#ifdef CONFIG_FRAC_SPLL
spll_debug(mtag | DBG_REF, s->dref_dt, 0);
spll_debug(mtag | DBG_TAG, s->dout_dt, 0);
#endif
spll_debug(mtag | DBG_ERR, err, 0);
spll_debug(mtag | DBG_SAMPLE_ID, s->sample_n++, 0);
spll_debug(mtag | DBG_Y, y, 1);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_PHASE_CURRENT, s->phase_shift_current, 0);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_PHASE_TARGET, s->phase_shift_target, 0);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_TIME_MS, timer_get_tics(), 0);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_REF, s->tag_ref + s->adder_ref, 0);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_TAG, s->tag_out + s->adder_out, 0);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_ERR, err, 0);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_SAMPLE_ID, s->sample_n++, 0);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_Y, y, 1);
s->tag_out = -1;
s->tag_ref = -1;
......@@ -372,7 +374,7 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
ld_update((spll_lock_det_t *)&s->ld, err);
if( s->ld.lock_changed)
spll_debug(DBG_EVENT | mtag, DBG_EVT_LOCKED, 1);
spll_debug(s->dbg_src_id, SPLL_DBG_SIGNAL_EVENT, SPLL_DBG_EVT_LOCK_ACQUIRED, 1);
mpll_handle_gain_schedule(s);
......
softpll/spll_main.h
View file @ 9e51f2e6
......@@ -46,6 +46,7 @@ struct spll_main_state {
int dac_index;
int enabled;
int ps_freeze, vco_freeze;
int dbg_src_id;
};
void mpll_init(struct spll_main_state *s, int id_ref,
......
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