swcore[generic-ing]: generic-azed hard-coded values (connected with rr_arbiter usage), identified limitation (in prio_encoder,TODO), added some description, tested with different port number values

swcore[generic-azing]: generic simulation (for any number of ports) works, cleaned up, added README to testbenches, changed names to add clarity to the naming

swcore[v2->v3 port]: a simple simulation for the wishbonized and wrapped (multiple times) swcore is working ... : sending/receiving few frames

swcore[v2->v3 port] wrappers for the wishbonized (xswc_core) swcore written, they enable the pWB emulators to talk to xswc_core (two wrappers needed). added simulation (xswc_core.sv) which instanciates 7 ports and wrapped xswc_core)

swcore[v2->v3 port]: added Tom's pWB<->WRF adapters into the wrapper, so we have a swcore which has pWB I/F, next step: change the simulation to test how it works

swcore[v2->v3 port]: simulation working for altera ip/genrams but cannot make it work for xilinx, leaving simulation with xilinx for later

swcore[v2->v3 port] the old simulation works (depending on some old code, e.g.: platform/genrams) that is not commited..