swcore[new mpm]: bugfixes in input block

modules/wrsw_swcore/xswc_input_block.vhd

@@ -1358,6 +1358,7 @@ architecture syn of xswc_input_block is
               ll_wr_req                <= '1';
               ll_entry.valid           <= '1';
               ll_entry.eof             <= '1';
+              ll_entry.addr            <= ll_fsm_addr;
               ll_entry.dsel            <= ll_fsm_dat_sel;
               ll_entry.size            <= ll_fsm_size;   
               -----------------------------------------------------------------------------------
@@ -1368,6 +1369,8 @@ architecture syn of xswc_input_block is
                 ll_entry.next_page       <= (others => '0');
                 ll_entry.next_page_valid <= '0';       
               end if;
+              ll_entry.oob_size        <= ll_fsm_oob_size;
+              ll_entry.oob_dsel        <= ll_fsm_oob_sel;                 
               s_ll_write               <= S_WRITE;                
             elsif(mpm_pg_req_d0 = '1') then
               if(interpck_page_in_advance = '1') then  -- normal write as if from READY_FOR_WR
@@ -1427,7 +1430,7 @@ architecture syn of xswc_input_block is
           when S_SOF_ON_WR =>
           --===========================================================================================
             if(ll_wr_req = '1' and ll_wr_done_i = '1') then -- written
-              if(pckstart_page_in_advance = '1') then
+              if(pckstart_page_in_advance = '1' and (ll_entry.next_page_valid = '0' or ll_entry.next_page/=pckstart_pageaddr)) then
                 ll_wr_req                <= '1';
                 ll_entry.valid           <= '0';
                 ll_entry.eof             <= '0';
@@ -1440,6 +1443,7 @@ architecture syn of xswc_input_block is
                 ll_entry.oob_dsel        <= ll_fsm_oob_sel;                        
                 s_ll_write               <= S_WRITE;
               else
+                ll_wr_req                <= '0';
                 s_ll_write               <= S_IDLE;
               end if;         
             end if;
@@ -1463,6 +1467,7 @@ architecture syn of xswc_input_block is
           when others =>
           --===========================================================================================    
              s_ll_write               <= S_IDLE;       
+             ll_wr_req                <= '1';
         end case;        
       end if;
     end if;

testbench/scb_top/main.sv

@@ -54,7 +54,7 @@ module main;
       EthPacketGenerator gen = new;
       EthPacket pkt, tmpl, pkt2;
       EthPacket arr[];
-      int i,j;
+      //int i,j;
       
       arr            = new[n_tries](arr);
 
@@ -73,27 +73,29 @@ module main;
       gen.set_size(63, 257);
 
       fork
-      for(i=0;i<n_tries;i++)
+      begin
+      for(int i=0;i<n_tries;i++)
            begin
               pkt  = gen.gen();
               pkt.oob = TX_FID;
               
               $display("Tx %d", i);
-              //   pkt.dump();
+              
               src.send(pkt);
               arr[i]  = pkt;
-
+              //pkt.dump();
             //  repeat(3000) @(posedge clk_sys);
               
 	  //    $display("Send: %d [dsize %d]", i+1,pkt.payload.size() + 14);
 	      
            end
-
-         for(j=0;j<n_tries;j++)
+         end 
+	begin
+         for(int j=0;j<n_tries;j++)
            begin
            sink.recv(pkt2);
 	      $display("rx %d", j);
-              
+              //pkt2.dump();
            if(unvid)
              arr[j].is_q  = 0;
            
@@ -104,10 +106,11 @@ module main;
                 arr[j].dump();
                 $display("Is: ");
                 pkt2.dump();
-                $fatal("dupa"); //ML
+               // $fatal("dupa"); //ML
            //sfp     $stop;
              end
            end // for (i=0;i<n_tries;i++)
+           end
          join
       seed = gen.get_seed();
       

testbench/swcore/Manifest.py

-target = "altera" # "xilinx" # 
+target = "xilinx" #  "altera" # 
 action = "simulation"
 
 #fetchto = "../../ip_cores"