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Commit 4c4bb5f1 authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[generic-ing]: almost fully generic (regarding number of ports) testbench

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modules/wrsw_swcore/swc_core.vhd
+ 82
− 478
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modules/wrsw_swcore/swc_swcore_pkg.vhd
+ 33
− 0
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......@@ -46,6 +46,7 @@ use ieee.math_real.log2;
library work;
use work.wr_fabric_pkg.all;
use work.wrsw_shared_types_pkg.all;
package swc_swcore_pkg is
......@@ -567,6 +568,38 @@ component swc_multiport_pck_pg_free_module is
);
end component;
component xswc_core is
generic(
g_mem_size : integer ;--:= c_swc_packet_mem_size
g_page_size : integer ;--:= c_swc_page_size
g_prio_num : integer ;--:= c_swc_output_prio_num;
g_max_pck_size : integer ;--:= c_swc_max_pck_size
g_num_ports : integer ;--:= c_swc_num_ports
g_data_width : integer ;--:= c_swc_data_width
g_ctrl_width : integer ; --:= c_swc_ctrl_width
g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
g_input_block_cannot_accept_data : string ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
g_output_block_per_prio_fifo_size : integer ; --:= c_swc_output_fifo_size (xswc_output_block)
-- probably useless with new memory
g_packet_mem_multiply : integer ;--:= c_swc_packet_mem_multiply (xswc_input_block, )
g_input_block_fifo_size : integer ;--:= c_swc_input_fifo_size (xswc_input_block)
g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in_array(g_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0)
);
end component;
end swc_swcore_pkg;
package body swc_swcore_pkg is
......
modules/wrsw_swcore/xswc_core.vhd
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testbench/swcore/Manifest.py
+ 3
− 1
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......@@ -8,7 +8,9 @@ action = "simulation"
files = [
"xswc_core_7_ports_wrapper.vhd",
"xswcore_wrapper.svh",
"xswc_core.sv"
"xswc_core.sv",
"xswcore_wrapper.v2.svh",
"xswc_core.v2.sv"
]
#vlog_opt="+incdir+../../../sim "
......
testbench/swcore/swc_param_defs.svh 0 → 100644
+ 24
− 0
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`ifndef __SWC_PARAM_DEFS_SV
`define __SWC_PARAM_DEFS_SV
`define c_mem_size 65536 //c_swc_packet_mem_size,
`define c_page_size 64 //c_swc_page_size,
`define c_prio_num 8 // c_swc_output_prio_num,
`define c_max_pck_size 10 * 1024 // 10kB -- c_swc_max_pck_size,
`define c_num_ports 7 //c_swc_num_ports,
`define c_data_width 16 //c_swc_data_width,
`define c_ctrl_width 4 //c_swc_ctrl_width,
`define c_pck_pg_free_fifo_size ((65536/64)/2) //c_swc_freeing_fifo_size,
`define c_input_block_cannot_accept_data "drop_pck" //"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
`define c_output_block_per_prio_fifo_size 64 //c_swc_output_fifo_size,
`define c_packet_mem_multiply 16 //c_swc_packet_mem_multiply,
`define c_input_block_fifo_size (2 * 16) //c_swc_input_fifo_size,
`define c_input_block_fifo_full_in_advance ((2 * 16) - 3) // c_swc_fifo_full_in_advance
`define array_copy(a, ah, al, b, bl) \
for (k=al; k<=ah; k=k+1) a[k] <= b[bl+k-al];
`define c_prio_num_width 3
`endif
\ No newline at end of file
testbench/swcore/xswc_core.sv
+ 179
− 29
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// Fabric emulator example, showing 2 fabric emulators connected together and exchanging packets.
`define c_clock_period 8
`define c_swc_page_addr_width 10
`define c_swc_usecount_width 4
`define c_wrsw_prio_width 3
`define c_swc_ctrl_width 4
`define c_swc_data_width 16
//`define c_wrsw_num_ports 11
`define c_wrsw_num_ports 7
`define c_n_pcks_to_send 10
`timescale 1ns / 1ps
......@@ -19,9 +18,6 @@
`include "xswcore_wrapper.svh"
`define array_copy(a, ah, al, b, bl) \
for (k=al; k<=ah; k=k+1) a[k] <= b[bl+k-al];
typedef struct {
int cnt;
......@@ -39,6 +35,10 @@ int global_seed = 0;
int pg_alloc_cnt[1024][20];
int pg_dealloc_cnt[1024][20];
EthPacket swc_matrix[`c_wrsw_num_ports][`c_n_pcks_to_send];
module main;
......@@ -72,7 +72,8 @@ module main;
IWishboneSlave #(2,16) U_wrf_sink_4 (clk,rst_n);
IWishboneSlave #(2,16) U_wrf_sink_5 (clk,rst_n);
IWishboneSlave #(2,16) U_wrf_sink_6 (clk,rst_n);
reg [`c_wrsw_num_ports-1:0] rtu_rsp_valid = 0;
wire [`c_wrsw_num_ports-1:0] rtu_rsp_ack;
reg [`c_wrsw_num_ports * `c_wrsw_num_ports - 1 : 0] rtu_dst_port_mask = 0;
......@@ -86,10 +87,12 @@ module main;
integer ports_ready = 0;
// some settings
integer n_packets_to_send = 100;
integer dbg = 0;
integer n_packets_to_send = `c_n_pcks_to_send;
integer dbg = 1;
xswcore_wrapper
DUT_xswcore_wrapper (
.clk_i (clk),
......@@ -190,7 +193,7 @@ module main;
tmpl.is_q = 0;
tmpl.src[0] = port;
gen.set_seed(global_seed++);
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /*| EthPacketGenerator::RX_OOB*/) ;
gen.set_template(tmpl);
gen.set_size(46, 1000);
......@@ -200,17 +203,24 @@ module main;
q.push_back(pkt);
set_rtu_rsp(port,1,drop /*drop*/,prio /*prio*/,mask /*mask*/);
set_rtu_rsp(port,1 /*valid*/,drop /*drop*/,prio /*prio*/,mask /*mask*/);
src[port].send(pkt);
if(dbg) $display("Sent @ port_%1d to mask=0x%x [with prio=%1d, drop=%1d ]!", port, mask, prio, drop);
if(drop == 0 && mask != 0)
begin
for(j=0;j<`c_wrsw_num_ports;j++)
begin
if(mask[j])
tx_cnt_by_port[port][j]++;
begin
tx_cnt_by_port[port][j]++;
swc_matrix[port][j] = pkt;
if(dbg) $display(" > port_%1d to port_%1d [pkt nr=%4d]", port, j, tx_cnt_by_port[port][j]);
end
end
end
if(dbg) $display("Sent:[@port_%1d, to mask=0x%x, with prio=%1d]!", port, mask, prio);
endtask // send_random_packets
......@@ -261,9 +271,9 @@ module main;
int i,j, cnt;
int sum_rx=0, sum_tx=1, sum_tx_by_port[11],sum_rx_by_port[11];
while(sum_tx != sum_rx)
begin
wait_cycles(80000);
// while(sum_tx != sum_rx)
// begin
for(i=0;i<11;i++)
begin
sum_tx_by_port[i] = 0;
......@@ -284,7 +294,7 @@ module main;
wait_cycles(50);
end
// end
$display("=============================================== DBG =================================================");
$display("Rx Ports : P 0 | P 1 | P 2 | P 3 | P 4 | P 5 | P 6 | P 7 | P 8 | P 9 | P10 | ");
......@@ -305,6 +315,38 @@ module main;
$display("SUM : sent pcks = %2d, received pcks = %2d", sum_tx,sum_rx);
$display("=================================== DBG ===============================");
cnt =0;
for(i=0;i<1024;i++)
if(dealloc_table[i].cnt!= alloc_table[i].cnt)
begin
$display("Page %4d: alloc = %4d [%2d:%2d|%2d:%2d|%2d:%2d|%2d:%2d|%2d:%2d|%2d:%2d]<=|=>dealloc = %4d [%2d:%11b|%2d:%11b|%2d:%11b|%2d:%11b|%2d:%11b|%2d:%11b] ",
i,
alloc_table[i].cnt,
alloc_table[i].usecnt[0], alloc_table[i].port[0],
alloc_table[i].usecnt[1], alloc_table[i].port[1],
alloc_table[i].usecnt[2], alloc_table[i].port[2],
alloc_table[i].usecnt[3], alloc_table[i].port[3],
alloc_table[i].usecnt[4], alloc_table[i].port[4],
alloc_table[i].usecnt[5], alloc_table[i].port[5],
dealloc_table[i].cnt,
dealloc_table[i].usecnt[0], dealloc_table[i].port[0],
dealloc_table[i].usecnt[1], dealloc_table[i].port[1],
dealloc_table[i].usecnt[2], dealloc_table[i].port[2],
dealloc_table[i].usecnt[3], dealloc_table[i].port[3],
dealloc_table[i].usecnt[4], dealloc_table[i].port[4],
dealloc_table[i].usecnt[5], dealloc_table[i].port[5]);
cnt++;
end
$display("=======================================================================");
if(cnt == 22)
$display("%4d pages allocated in advance (port X start_of_pck + port X pck_internal pages)", cnt);
else
$display("MEM LEAKGE Report: number of lost pages = %2d", (cnt - (2*`c_wrsw_num_ports)));
$display("=================================== DBG ===============================");
$fatal("dupa");
end
......@@ -331,7 +373,7 @@ module main;
EthPacket pkt, tmpl;
EthPacket txed[$];
EthPacketGenerator gen;
int i;
src = new[7];
sink = new[7];
......@@ -342,7 +384,8 @@ module main;
src[4] = new(U_wrf_source_4.get_accessor());
src[5] = new(U_wrf_source_5.get_accessor());
src[6] = new(U_wrf_source_6.get_accessor());
// U_wrf_sink_1.permanent_stall_enable();
sink[0] = new(U_wrf_sink_0.get_accessor());
sink[1] = new(U_wrf_sink_1.get_accessor());
......@@ -352,13 +395,34 @@ module main;
sink[5] = new(U_wrf_sink_5.get_accessor());
sink[6] = new(U_wrf_sink_6.get_accessor());
gen = new;
// for(i = 0;i<`c_wrsw_num_ports ;i++)
// rtu_rsp_valid[i] = 1;
@(posedge rst_n);
@(posedge clk);
wait_cycles(50);
wait_cycles(500);
ports_ready = 1; // let now the ports to start sending
// ports_ready = 1; // let now the ports to start sending
//load_port(src, 0, n_packets_to_send);
send_random_packet(src,txed, 0 /*port*/, 0 /*drop*/,7 /*prio*/, 2 /*mask*/);
// send_random_packet(src,txed, 0, 0,7 , 3);
// send_random_packet(src,txed, 0, 1,7 , 3);
// send_random_packet(src,txed, 0, 0,7 , 3);
// send_random_packet(src,txed, 0, 0,7 , 3);
for(i=0; i<1000; i++)
begin
send_random_packet(src,txed, i%7, 0,7 , 7);
// if(! i%10) U_wrf_source_0.error_on_byte(10);
// else U_wrf_source_0.error_on_byte(0);
wait_cycles(500);
/* if(i==80)
U_wrf_sink_1.permanent_stall_disable();*/
end
wait_cycles(500);
......@@ -410,49 +474,135 @@ module main;
EthPacket pkt;
sink[0].recv(pkt);
rx_cnt_by_port[pkt.src[0]][0]++;
if(dbg) $display("Received @ port_%1d from port_%1d",0, pkt.src[0]);
if(dbg) $display("Received @ port_%1d from port_%1d [pkt nr=%4d]",0, pkt.src[0],rx_cnt_by_port[pkt.src[0]][0]);
end
always @(posedge clk) if (sink[1].poll())
always @(posedge clk) if(sink[1].poll())
begin
EthPacket pkt;
sink[1].recv(pkt);
rx_cnt_by_port[pkt.src[0]][1]++;
if(dbg) $display("Received @ port_%1d from port_%1d",1, pkt.src[0]);
if(dbg) $display("Received @ port_%1d from port_%1d [pkt nr=%4d]",1, pkt.src[0],rx_cnt_by_port[pkt.src[0]][1]);
end
always @(posedge clk) if (sink[2].poll())
begin
EthPacket pkt;
sink[2].recv(pkt);
rx_cnt_by_port[pkt.src[0]][2]++;
if(dbg) $display("Received @ port_%1d from port_%1d",2, pkt.src[0]);
if(dbg) $display("Received @ port_%1d from port_%1d [pkt nr=%4d]",2, pkt.src[0],rx_cnt_by_port[pkt.src[0]][2]);
end
always @(posedge clk) if (sink[3].poll())
begin
EthPacket pkt;
sink[3].recv(pkt);
rx_cnt_by_port[pkt.src[0]][3]++;
if(dbg) $display("Received @ port_%1d from port_%1d",3, pkt.src[0]);
if(dbg) $display("Received @ port_%1d from port_%1d [pkt nr=%4d]",3, pkt.src[0],rx_cnt_by_port[pkt.src[0]][3]);
end
always @(posedge clk) if (sink[4].poll())
begin
EthPacket pkt;
sink[4].recv(pkt);
rx_cnt_by_port[pkt.src[0]][4]++;
if(dbg) $display("Received @ port_%1d from port_%1d",4, pkt.src[0]);
if(dbg) $display("Received @ port_%1d from port_%1d [pkt nr=%4d]",4, pkt.src[0],rx_cnt_by_port[pkt.src[0]][4]);
end
always @(posedge clk) if (sink[5].poll())
begin
EthPacket pkt;
sink[5].recv(pkt);
rx_cnt_by_port[pkt.src[0]][5]++;
if(dbg) $display("Received @ port_%1d from port_%1d",5, pkt.src[0]);
if(dbg) $display("Received @ port_%1d from port_%1d [pkt nr=%4d]",5, pkt.src[0],rx_cnt_by_port[pkt.src[0]][5]);
end
always @(posedge clk) if (sink[5].poll())
begin
EthPacket pkt;
sink[6].recv(pkt);
rx_cnt_by_port[pkt.src[0]][6]++;
if(dbg) $display("Received @ port_%1d from port_%1d",6, pkt.src[0]);
if(dbg) $display("Received @ port_%1d from port_%1d [pkt nr=%4d]",6, pkt.src[0],rx_cnt_by_port[pkt.src[0]][6]);
end
///////////////////////////////////////////////////////////////////////////////////////////////////////
///////// Monitoring allocation of pages /////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
// always @(posedge clk) if(DUT.memory_management_unit.pg_addr_valid)
always @(posedge clk) if(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_alloc & DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_done)
begin
int address;
int usecnt;
usecnt = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_usecnt;
wait(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_addr_valid);
address = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_addr_alloc;
pg_alloc_cnt[address][pg_alloc_cnt[address][0]+1]= usecnt;
pg_alloc_cnt[address][0]++;
alloc_table[address].usecnt[alloc_table[address].cnt] = usecnt;
alloc_table[address].port[alloc_table[address].cnt] = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.in_sel;
alloc_table[address].cnt++;
end
///////////////////////////////////////////////////////////////////////////////////////////////////////
///////// Monitoring deallocation of pages /////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) if(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.alloc_core.tmp_dbg_dealloc)
begin
int address;
address = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.alloc_core.tmp_page;
pg_dealloc_cnt[address][0]++;
dealloc_table[address].cnt++;
end
///////////////////////////////////////////////////////////////////////////////////////////////////////
///////// Monitoring freeing of pages /////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) if(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_free & DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_done)
begin
int address;
int port_mask;
int port;
port = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.in_sel;
address = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_addr;
port_mask = dealloc_table[address].port[dealloc_table[address].cnt ] ;
pg_dealloc_cnt[address][pg_dealloc_cnt[address][0] + 1]++;
dealloc_table[address].port[dealloc_table[address].cnt ] = ((1 << port) | port_mask) & 'h7FF;
dealloc_table[address].usecnt[dealloc_table[address].cnt ]++;
end
///////////////////////////////////////////////////////////////////////////////////////////////////////
///////// Monitoring setting of pages' usecnt /////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) if(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_set_usecnt & DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_done)
begin
int address;
address = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_addr;
pg_alloc_cnt[address][pg_alloc_cnt[address][0] + 1] = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_usecnt;
alloc_table[address].usecnt[alloc_table[address].cnt - 1] = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_usecnt;;
end
endmodule // main
testbench/swcore/xswc_core.v2.sv 0 → 100644
+ 540
− 0
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testbench/swcore/xswcore_wrapper.svh
+ 30
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`define PORT_NUMBER 7
`define PORT_PRIO_W 3
`define array_copy(a, ah, al, b, bl) \
for (k=al; k<=ah; k=k+1) a[k] <= b[bl+k-al];
`define WIRE_WB_SINK(iface, nr, prefix) \
.prefix``_adr_``nr``_i(iface.adr), \
......@@ -33,22 +34,22 @@ module xswcore_wrapper
input rst_n_i,
// input to the wrapper, this is connected to the sink of the xswc_core
IWishboneMaster.master src_0,
IWishboneMaster.master src_1,
IWishboneMaster.master src_2,
IWishboneMaster.master src_3,
IWishboneMaster.master src_4,
IWishboneMaster.master src_5,
IWishboneMaster.master src_6,
IWishboneMaster.master src_0,
IWishboneMaster.master src_1,
IWishboneMaster.master src_2,
IWishboneMaster.master src_3,
IWishboneMaster.master src_4,
IWishboneMaster.master src_5,
IWishboneMaster.master src_6,
// output of the wrapper, this is connected to the source of the xswc_core
IWishboneSlave.slave snk_0,
IWishboneSlave.slave snk_1,
IWishboneSlave.slave snk_2,
IWishboneSlave.slave snk_3,
IWishboneSlave.slave snk_4,
IWishboneSlave.slave snk_5,
IWishboneSlave.slave snk_6,
IWishboneSlave.slave snk_0,
IWishboneSlave.slave snk_1,
IWishboneSlave.slave snk_2,
IWishboneSlave.slave snk_3,
IWishboneSlave.slave snk_4,
IWishboneSlave.slave snk_5,
IWishboneSlave.slave snk_6,
input [`PORT_NUMBER-1 :0] rtu_rsp_valid_i,
......@@ -69,21 +70,21 @@ module xswcore_wrapper
.rst_n_i (rst_n_i),
`WIRE_WB_SINK(src_0, 0, snk),
`WIRE_WB_SINK(src_1, 1, snk),
`WIRE_WB_SINK(src_2, 2, snk),
`WIRE_WB_SINK(src_3, 3, snk),
`WIRE_WB_SINK(src_4, 4, snk),
`WIRE_WB_SINK(src_5, 5, snk),
`WIRE_WB_SINK(src_6, 6, snk),
`WIRE_WB_SINK(src[0], 0, snk),
`WIRE_WB_SINK(src[1], 1, snk),
`WIRE_WB_SINK(src[2], 2, snk),
`WIRE_WB_SINK(src[3], 3, snk),
`WIRE_WB_SINK(src[4], 4, snk),
`WIRE_WB_SINK(src[5], 5, snk),
`WIRE_WB_SINK(src[6], 6, snk),
`WIRE_WB_SOURCE(snk_0, 0, src),
`WIRE_WB_SOURCE(snk_1, 1, src),
`WIRE_WB_SOURCE(snk_2, 2, src),
`WIRE_WB_SOURCE(snk_3, 3, src),
`WIRE_WB_SOURCE(snk_4, 4, src),
`WIRE_WB_SOURCE(snk_5, 5, src),
`WIRE_WB_SOURCE(snk_6, 6, src),
`WIRE_WB_SOURCE(snk[0], 0, src),
`WIRE_WB_SOURCE(snk[1], 1, src),
`WIRE_WB_SOURCE(snk[2], 2, src),
`WIRE_WB_SOURCE(snk[3], 3, src),
`WIRE_WB_SOURCE(snk[4], 4, src),
`WIRE_WB_SOURCE(snk[5], 5, src),
`WIRE_WB_SOURCE(snk[6], 6, src),
.rtu_rsp_valid_i (rtu_rsp_valid_i),
.rtu_rsp_ack_o (rtu_rsp_ack_o),
......
testbench/swcore/xswcore_wrapper.v2.svh 0 → 100644
+ 134
− 0
View file @ 4c4bb5f1
`include "swc_param_defs.svh"
`define array_assign(a, ah, al, b, bl) \
for (k=al; k<=ah; k=k+1) begin assign a[k] = b[bl+k-al]; end
module xswcore_wrapper_v2
(
clk_i,
rst_n_i,
src,
snk,
rtu_rsp_valid_i,
rtu_rsp_ack_o,
rtu_dst_port_mask_i,
rtu_drop_i,
rtu_prio_i
);
input clk_i;
input rst_n_i;
IWishboneMaster #(2,16) src[`c_num_ports] (clk_i,rst_n_i);
IWishboneSlave #(2,16) snk[`c_num_ports] (clk_i,rst_n_i);
input [`c_num_ports-1 :0] rtu_rsp_valid_i;
output [`c_num_ports-1 :0] rtu_rsp_ack_o;
input [`c_num_ports*`c_num_ports-1 :0] rtu_dst_port_mask_i;
input [`c_num_ports-1 :0] rtu_drop_i;
input [`c_num_ports*3-1 :0] rtu_prio_i;
wire [`c_num_ports*16 -1 :0] snk_dat ;
wire [`c_num_ports*2 -1 :0] snk_adr ;
wire [`c_num_ports*2 -1 :0] snk_sel ;
wire [`c_num_ports -1 :0] snk_cyc ;
wire [`c_num_ports -1 :0] snk_stb ;
wire [`c_num_ports -1 :0] snk_we ;
wire [`c_num_ports -1 :0] snk_stall;
wire [`c_num_ports -1 :0] snk_ack ;
wire [`c_num_ports -1 :0] snk_err ;
wire [`c_num_ports -1 :0] snk_rty ;
wire [`c_num_ports*16 -1 :0] src_dat ;
wire [`c_num_ports*2 -1 :0] src_adr ;
wire [`c_num_ports*2 -1 :0] src_sel ;
wire [`c_num_ports -1 :0] src_cyc ;
wire [`c_num_ports -1 :0] src_stb ;
wire [`c_num_ports -1 :0] src_we ;
wire [`c_num_ports -1 :0] src_stall;
wire [`c_num_ports -1 :0] src_ack ;
wire [`c_num_ports -1 :0] src_err ;
swc_core
#(
.g_mem_size (`c_mem_size),
.g_page_size (`c_page_size),
.g_prio_num (`c_prio_num),
.g_max_pck_size (`c_max_pck_size),
.g_num_ports (`c_num_ports),
.g_data_width (`c_data_width),
.g_ctrl_width (`c_ctrl_width),
.g_pck_pg_free_fifo_size (`c_pck_pg_free_fifo_size),
.g_input_block_cannot_accept_data (`c_input_block_cannot_accept_data),
.g_output_block_per_prio_fifo_size (`c_output_block_per_prio_fifo_size),
.g_packet_mem_multiply (`c_packet_mem_multiply),
.g_input_block_fifo_size (`c_input_block_fifo_size),
.g_input_block_fifo_full_in_advance (`c_input_block_fifo_full_in_advance)
) DUT_swc_core(
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.snk_dat_i (snk_dat),
.snk_adr_i (snk_adr),
.snk_sel_i (snk_sel),
.snk_cyc_i (snk_cyc),
.snk_stb_i (snk_stb),
.snk_we_i (snk_we),
.snk_stall_o (snk_stall),
.snk_ack_o (snk_ack),
.snk_err_o (snk_err),
.snk_rty_o (snk_rty),
.src_dat_o (src_dat),
.src_adr_o (src_adr),
.src_sel_o (src_sel),
.src_cyc_o (src_cyc),
.src_stb_o (src_stb),
.src_we_o (src_we),
.src_stall_i (src_stall),
.src_ack_i (src_ack),
.src_err_i (src_err),
.rtu_rsp_valid_i (rtu_rsp_valid_i),
.rtu_rsp_ack_o (rtu_rsp_ack_o),
.rtu_dst_port_mask_i (rtu_dst_port_mask_i),
.rtu_drop_i (rtu_drop_i),
.rtu_prio_i (rtu_prio_i)
);
genvar i, k;
generate
for(i=0;i<`c_num_ports;i=i+1)
begin
`array_assign(snk_dat,(i+1)*16-1, i*16,src[i].dat_o,0);
`array_assign(snk_adr,(i+1)*2 -1, i*2 ,src[i].adr,0);
`array_assign(snk_sel,(i+1)*2 -1 ,i*2 ,src[i].sel,0);
assign snk_cyc[i] = src[i].cyc;
assign snk_stb[i] = src[i].stb;
assign snk_we[i] = src[i].we;
assign src[i].stall = snk_stall[i];
assign src[i].ack = snk_ack[i];
assign src[i].err = snk_err[i];
assign src[i].rty = snk_rty[i];
`array_assign(snk[i].dat_i,15,0,src_dat,i*16);
`array_assign(snk[i].adr ,1, 0,src_adr,i*2);
`array_assign(snk[i].sel ,1, 0,src_sel,i*2);
assign snk[i].cyc = src_cyc[i];
assign snk[i].stb = src_stb[i];
assign snk[i].we = src_we[i];
assign src_stall[i] = snk[i].stall;
assign src_ack[i] = snk[i].ack;
assign src_err[i] = snk[i].err;
end //for(i=0;i<`c_num_ports;i=i+1)
endgenerate
endmodule
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