swcore[v2->v3 port]: simulation working for altera ip/genrams but cannot make...

swcore[v2->v3 port]: simulation working for altera ip/genrams but cannot make it work for xilinx, leaving simulation with xilinx for later

testbench/swcore/Manifest.py

-target = "altera" #"xilinx" # 
+target = "altera" # "xilinx" # 
 action = "simulation"
 
 #fetchto = "../../ip_cores"
@@ -9,8 +9,6 @@ vlog_opt="+incdir+../../../sim "
 
 modules = {"local":
 		[ 
-		  #"../../platform/altera",
-		  #"../../platform/genrams/altera",
 		  "../../ip_cores/general-cores/modules/genrams/",
 		  "../../modules/wrsw_swcore",
 		],