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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit e6b48288 authored by Marek Gumiński's avatar Marek Gumiński
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Changed defaults of some components to values used in 18 port wrs. 

Simplifies synthesis of separate blocks.
parent 19dbcf87
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Showing with 10 additions and 10 deletions
ip_cores/wr-cores-local/modules/wr_endpoint/xwr_endpoint.vhd
View file @ e6b48288
......@@ -46,27 +46,27 @@ use work.wishbone_pkg.all;
entity xwr_endpoint is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_simulation : boolean := false;
g_tx_force_gap_length : integer := 0;
g_tx_runt_padding : boolean := false;
g_pcs_16bit : boolean := false;
g_pcs_16bit : boolean := true;
g_records_for_phy : boolean := false;
g_rx_buffer_size : integer := 1024;
g_with_rx_buffer : boolean := true;
g_with_flow_control : boolean := true;
g_with_flow_control : boolean := false;
g_with_timestamper : boolean := true;
g_with_dpi_classifier : boolean := true;
g_with_vlans : boolean := true;
g_with_rtu : boolean := true;
g_with_leds : boolean := true;
g_with_dmtd : boolean := true;
g_with_dmtd : boolean := false;
g_with_packet_injection : boolean := false;
g_use_new_rxcrc : boolean := false;
g_use_new_rxcrc : boolean := true;
g_use_new_txcrc : boolean := false;
g_with_stop_traffic : boolean := false;
g_ep_idx : integer
g_with_stop_traffic : boolean := true;
g_ep_idx : integer := 0
);
port (
......
top/bare_top/scb_top_bare.vhd
View file @ e6b48288
......@@ -55,7 +55,7 @@ use UNISIM.vcomponents.all;
entity scb_top_bare is
generic(
g_num_ports : integer := 6;
g_num_ports : integer := 18;
g_simulation : boolean := false;
g_without_network : boolean := false;
g_with_TRU : boolean := false;
......@@ -64,7 +64,7 @@ entity scb_top_bare is
g_with_PSTATS : boolean := true;
g_with_muxed_CS : boolean := false;
g_with_PSU : boolean := false;
g_with_watchdog : boolean := false;
g_with_watchdog : boolean := true;
g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0')
);
port (
......
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