Project Description
The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA (MPSoC XCZU11EG-1FFVC1156E).
Results
Based on the code in this repository, a short report was prepared: WRS resource utilisation on Xilinx US+ FPGA (see doc/report/
in the repository).
Result utilization for of switch HDL on Xilinx Ultrascale+ FPGA is presented below (details in the report):
Switch with 1GbE and no redundancy features (proposed_master) - post-synthesis report
Switch with 1GbE and redundancy features (data and timing) - post-synthesis report
Switch with 10GbE and no redundancy features - post-synthesis report
Switch with 10GbE and redundancy features (data and timing)
General question about project
- Maciej Lipinski - CERN
- Marek Guminski - Creotech
Status
Date | Event |
---|---|
01-08-2019 | Project started |
23-08-2019 | 1Gb version (without and with redundancy features) synthesized for US+ (repoted in conf-call) |
06-09-2019 | 10Gb version (without and with redundancy features) synthesized for US+ (repoted in conf-call) |
09-09-2019 | Project with documentation delivered to CERN for feedback |
09-10-2019 | Final version approved by CERN - project closed |