Changed clock frequency definitions.

720c1d3f · Marek Gumiński · 02e63867 · 720c1d3f
Commit 720c1d3f authored Sep 12, 2019 by Marek Gumiński
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scb_top_synthesis.xdc top/scb_18ports/scb_top_synthesis.xdc +7 -7

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--- a/top/scb_18ports/scb_top_synthesis.xdc
+++ b/top/scb_18ports/scb_top_synthesis.xdc

 create_clock -period 40.000 -name clk_boot -waveform {0.000 20.000} [get_ports fpga_clk_25mhz_p_i]
-create_clock -period 16.000 -name clk_dmtd -waveform {0.000 8.000} [get_ports fpga_clk_dmtd_p_i]
-create_clock -period 16.000 -name clk_ref -waveform {0.000 8.000} [get_ports fpga_clk_ref_p_i]
+create_clock -period 6.4000 -name clk_dmtd -waveform {0.000 3.200} [get_ports fpga_clk_dmtd_p_i]
+create_clock -period 6.4000 -name clk_ref -waveform {0.000 3.200} [get_ports fpga_clk_ref_p_i]



-create_clock -period 8.000 -name clk_gtx_0 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[0]}]
-create_clock -period 8.000 -name clk_gtx_1 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[1]}]
-create_clock -period 8.000 -name clk_gtx_2 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[2]}]
-create_clock -period 8.000 -name clk_gtx_3 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[3]}]
-create_clock -period 8.000 -name clk_gtx_4 -waveform {0.000 4.000} [get_ports {gtx_clk_p_i[4]}]
+create_clock -period 6.400 -name clk_gtx_0 -waveform {0.000 3.200} [get_ports {gtx_clk_p_i[0]}]
+create_clock -period 6.400 -name clk_gtx_1 -waveform {0.000 3.200} [get_ports {gtx_clk_p_i[1]}]
+create_clock -period 6.400 -name clk_gtx_2 -waveform {0.000 3.200} [get_ports {gtx_clk_p_i[2]}]
+create_clock -period 6.400 -name clk_gtx_3 -waveform {0.000 3.200} [get_ports {gtx_clk_p_i[3]}]
+create_clock -period 6.400 -name clk_gtx_4 -waveform {0.000 3.200} [get_ports {gtx_clk_p_i[4]}]