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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 47561189 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Marek Gumiński
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SPLL: communiating status of ports (up/down) directly to SoftPLL

parent 5745da33
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Showing with 14 additions and 1 deletion
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 47561189
......@@ -125,6 +125,10 @@ entity wrsw_rt_subsystem is
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
-- bit per rx clock, indicates whether the clocks are OK (UP) or not reliabie (DOWN)
-- used for switchover between them
clk_rx_status_i : in std_logic_vector(g_num_rx_clocks-1 downto 0) :=(others=>'0');
-- Debug
spll_dbg_o : out std_logic_vector(5 downto 0)
);
......@@ -166,6 +170,7 @@ architecture rtl of wrsw_rt_subsystem is
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
......@@ -355,6 +360,7 @@ begin -- rtl
out_locked_o => open,
slave_i => cnx_master_out(c_SLAVE_SOFTPLL),
slave_o => cnx_master_in(c_SLAVE_SOFTPLL),
clk_rx_status_i => clk_rx_status_i,
int_o => cpu_irq_vec(0),
debug_o => spll_dbg_o);
......
top/bare_top/scb_top_bare.vhd
View file @ 47561189
......@@ -445,6 +445,8 @@ architecture rtl of scb_top_bare is
signal nic_rtu_rsp : t_rtu_response;
signal nic_rtu_ack : std_logic;
signal ep_port_status : std_logic_vector(g_num_ports-1 downto 0);
begin
......@@ -630,6 +632,7 @@ begin
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
clk_rx_status_i => ep_port_status,
spll_dbg_o => spll_dbg_o);
ppsdel_tap_out <= ppsdel_tap_wide_out(8 downto 4);
......@@ -845,6 +848,8 @@ begin
clk_rx_vec(i) <= phys_i(i).rx_clk;
ep_port_status(i) <= ep2tru(i).status;
end generate gen_endpoints_and_phys;
GEN_TIMING: for I in 0 to c_NUM_PORTS generate
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 47561189
......@@ -249,7 +249,8 @@ package wrsw_components_pkg is
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic);
pll_reset_n_o : out std_logic;
clk_rx_status_i : in std_logic_vector(g_num_rx_clocks-1 downto 0) :=(others=>'0'));
end component;
component chipscope_icon
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 47561189
......@@ -254,6 +254,7 @@ package wrsw_top_pkg is
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
clk_rx_status_i : in std_logic_vector(g_num_rx_clocks-1 downto 0) :=(others=>'0');
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......
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