adding difault value of new scb_top_bare.vhd input so that all the old stuff…

adding difault value of new scb_top_bare.vhd input so that all the old stuff works fine (e.g. simulation)

adding difault value of new scb_top_bare.vhd input so that all the old stuff…
adding difault value of new scb_top_bare.vhd input so that all the old stuff works fine (e.g. simulation)
5745da33 · Maciej Lipinski · Marek Gumiński · aa825a3f · 5745da33
Commit 5745da33 authored Oct 15, 2014 by Maciej Lipinski Committed by Marek Gumiński Aug 19, 2019
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scb_top_bare.vhd top/bare_top/scb_top_bare.vhd +1 -1

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--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -82,7 +82,7 @@ entity scb_top_bare is
    -- for re-phasing the 10 MHz input as well as clocking the 
    clk_aux_i : in std_logic;

-		clk_ext_mul_i	:	in std_logic;
+		clk_ext_mul_i	:	in std_logic :='0';
 		clk_ext_mul_locked_i	:	in std_logic;

    clk_aux_p_o  : out std_logic; -- going to CLK2 SMC on the front pannel, by