- 08 Aug, 2017 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 07 Jul, 2017 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
compiled from commit: 25f814a3 update ppsi to fix 1-pps generation in Master mode
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- 06 Jul, 2017 2 commits
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Maciej Lipinski authored
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Grzegorz Daniluk authored
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- 04 Jul, 2017 7 commits
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Grzegorz Daniluk authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
PPS csync is asserted one 125MHz ref clock cycle before the actual PPS. It can be used for aligning another signal to the PPS.
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Dimitris Lampridis authored
platform/xilinx: add generics to Xilinx platform to select which GTP channel to use (defaults to ch1)
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Dimitris Lampridis authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
wrpc-sw binaries compiled from commit: a2dd8bb9: spec_defconfig: remove spaces from built-in init script
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- 30 Jun, 2017 6 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Peter Jansweijer authored
txts -> dio_p/n_o[2] (= Lemo 3) rxts -> dio_p/n_o[1] (= Lemo 2; formerly used for 62.5 MHz RefClk)
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Peter Jansweijer authored
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Peter Jansweijer authored
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Grzegorz Daniluk authored
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- 26 Jun, 2017 1 commit
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Denia Bouhired-Ferrag authored
Since generic fifo has been fixed in general cores, the threshold values have been corrected accordingle and the threshold for transmission needn't have an offset to work
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- 23 Jun, 2017 3 commits
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Grzegorz Daniluk authored
wrpc-sw: 24ebdb55: print also built-in init script with _init show_ cmd
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 22 Jun, 2017 2 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 20 Jun, 2017 3 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 19 Jun, 2017 12 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Final version of the testbench.Fully working with 6 different tests: flush, timeout, tx_thr, tx_max words, fxd latency, drop frames.
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Changed data type block so it no longer has wrd_cnt, first and last_wrd fields. Not really required anymore
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Working testbench. Runs 5 tests. Bug: does not cope with multiple block frames. only single block frames.
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