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White Rabbit core collection
Commit dcd569f8 authored by Maciej Lipinski's avatar Maciej Lipinski
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[wbgen-ver] updated diags to have version of the wbgen registers

parent dd82e961
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modules/wrc_core/wrc_diags_pkg.vhd
View file @ dcd569f8
......@@ -3,7 +3,8 @@
---------------------------------------------------------------------------------------
-- File : wrc_diags_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
-- Created : Tue Apr 25 12:14:42 2017
-- Created : Tue Jun 20 09:59:03 2017
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
......@@ -70,10 +71,12 @@ package wrc_diags_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_wrc_diags_out_registers is record
ver_id_o : std_logic_vector(31 downto 0);
ctrl_data_snapshot_o : std_logic;
end record;
constant c_wrc_diags_out_registers_init_value: t_wrc_diags_out_registers := (
ver_id_o => (others => '0'),
ctrl_data_snapshot_o => '0'
);
function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers;
......
modules/wrc_core/wrc_diags_wb.vhd
View file @ dcd569f8
......@@ -3,7 +3,8 @@
---------------------------------------------------------------------------------------
-- File : wrc_diags_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
-- Created : Tue Apr 25 12:14:42 2017
-- Created : Tue Jun 20 09:59:03 2017
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
......@@ -37,26 +38,17 @@ end wrc_diags_wb;
architecture syn of wrc_diags_wb is
signal wrc_diags_ver_id_int : std_logic_vector(31 downto 0);
signal wrc_diags_ctrl_data_snapshot_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -65,6 +57,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
wrc_diags_ver_id_int <= "00000000000000000000000000000001";
wrc_diags_ctrl_data_snapshot_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -79,6 +72,13 @@ begin
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
wrc_diags_ver_id_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= wrc_diags_ver_id_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
wrc_diags_ctrl_data_snapshot_int <= wrdata_reg(8);
end if;
......@@ -116,7 +116,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
when "00010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.wdiag_sstat_wr_mode_i;
......@@ -150,7 +150,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
when "00011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.wdiag_pstat_link_i;
......@@ -187,7 +187,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
when "00100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.wdiag_ptpstat_ptpstate_i;
......@@ -217,7 +217,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
when "00101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.wdiag_astat_aux_i;
......@@ -247,85 +247,85 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
when "00110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_txfcnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
when "00111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_rxfcnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
when "01000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_sec_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
when "01001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_sec_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
when "01010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_ns_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
when "01011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_mu_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
when "01100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_mu_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
when "01101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_dms_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
when "01110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_dms_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
when "01111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_asym_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
when "10000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_cko_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
when "10001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_setp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
when "10010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_ucnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
when "10011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_temp_i;
......@@ -344,6 +344,8 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Version identifier
regs_o.ver_id_o <= wrc_diags_ver_id_int;
-- WR DIAG data valid
-- WR DIAG data snapshot
regs_o.ctrl_data_snapshot_o <= wrc_diags_ctrl_data_snapshot_int;
......
modules/wrc_core/wrc_diags_wb.wb
View file @ dcd569f8
......@@ -5,6 +5,7 @@ peripheral {
description = "Diagnostics information accessible via WR";
prefix = "wrc_diags";
hdl_entity = "wrc_diags_wb";
version = 1;
reg {
name = "Ctrl";
......
sim/wrc_diags_regs.vh
View file @ dcd569f8
`define ADDR_WRC_DIAGS_CTRL 7'h0
`define WBGEN2_WRC_DIAGS_VERSION 32'h00000001
`define ADDR_WRC_DIAGS_VER 7'h0
`define WRC_DIAGS_VER_ID_OFFSET 0
`define WRC_DIAGS_VER_ID 32'hffffffff
`define ADDR_WRC_DIAGS_CTRL 7'h4
`define WRC_DIAGS_CTRL_DATA_VALID_OFFSET 0
`define WRC_DIAGS_CTRL_DATA_VALID 32'h00000001
`define WRC_DIAGS_CTRL_DATA_SNAPSHOT_OFFSET 8
`define WRC_DIAGS_CTRL_DATA_SNAPSHOT 32'h00000100
`define ADDR_WRC_DIAGS_WDIAG_SSTAT 7'h4
`define ADDR_WRC_DIAGS_WDIAG_SSTAT 7'h8
`define WRC_DIAGS_WDIAG_SSTAT_WR_MODE_OFFSET 0
`define WRC_DIAGS_WDIAG_SSTAT_WR_MODE 32'h00000001
`define WRC_DIAGS_WDIAG_SSTAT_SERVOSTATE_OFFSET 8
`define WRC_DIAGS_WDIAG_SSTAT_SERVOSTATE 32'h00000f00
`define ADDR_WRC_DIAGS_WDIAG_PSTAT 7'h8
`define ADDR_WRC_DIAGS_WDIAG_PSTAT 7'hc
`define WRC_DIAGS_WDIAG_PSTAT_LINK_OFFSET 0
`define WRC_DIAGS_WDIAG_PSTAT_LINK 32'h00000001
`define WRC_DIAGS_WDIAG_PSTAT_LOCKED_OFFSET 1
`define WRC_DIAGS_WDIAG_PSTAT_LOCKED 32'h00000002
`define ADDR_WRC_DIAGS_WDIAG_PTPSTAT 7'hc
`define ADDR_WRC_DIAGS_WDIAG_PTPSTAT 7'h10
`define WRC_DIAGS_WDIAG_PTPSTAT_PTPSTATE_OFFSET 0
`define WRC_DIAGS_WDIAG_PTPSTAT_PTPSTATE 32'h000000ff
`define ADDR_WRC_DIAGS_WDIAG_ASTAT 7'h10
`define ADDR_WRC_DIAGS_WDIAG_ASTAT 7'h14
`define WRC_DIAGS_WDIAG_ASTAT_AUX_OFFSET 0
`define WRC_DIAGS_WDIAG_ASTAT_AUX 32'h000000ff
`define ADDR_WRC_DIAGS_WDIAG_TXFCNT 7'h14
`define ADDR_WRC_DIAGS_WDIAG_RXFCNT 7'h18
`define ADDR_WRC_DIAGS_WDIAG_SEC_MSB 7'h1c
`define ADDR_WRC_DIAGS_WDIAG_SEC_LSB 7'h20
`define ADDR_WRC_DIAGS_WDIAG_NS 7'h24
`define ADDR_WRC_DIAGS_WDIAG_MU_MSB 7'h28
`define ADDR_WRC_DIAGS_WDIAG_MU_LSB 7'h2c
`define ADDR_WRC_DIAGS_WDIAG_DMS_MSB 7'h30
`define ADDR_WRC_DIAGS_WDIAG_DMS_LSB 7'h34
`define ADDR_WRC_DIAGS_WDIAG_ASYM 7'h38
`define ADDR_WRC_DIAGS_WDIAG_CKO 7'h3c
`define ADDR_WRC_DIAGS_WDIAG_SETP 7'h40
`define ADDR_WRC_DIAGS_WDIAG_UCNT 7'h44
`define ADDR_WRC_DIAGS_WDIAG_TEMP 7'h48
`define ADDR_WRC_DIAGS_WDIAG_TXFCNT 7'h18
`define ADDR_WRC_DIAGS_WDIAG_RXFCNT 7'h1c
`define ADDR_WRC_DIAGS_WDIAG_SEC_MSB 7'h20
`define ADDR_WRC_DIAGS_WDIAG_SEC_LSB 7'h24
`define ADDR_WRC_DIAGS_WDIAG_NS 7'h28
`define ADDR_WRC_DIAGS_WDIAG_MU_MSB 7'h2c
`define ADDR_WRC_DIAGS_WDIAG_MU_LSB 7'h30
`define ADDR_WRC_DIAGS_WDIAG_DMS_MSB 7'h34
`define ADDR_WRC_DIAGS_WDIAG_DMS_LSB 7'h38
`define ADDR_WRC_DIAGS_WDIAG_ASYM 7'h3c
`define ADDR_WRC_DIAGS_WDIAG_CKO 7'h40
`define ADDR_WRC_DIAGS_WDIAG_SETP 7'h44
`define ADDR_WRC_DIAGS_WDIAG_UCNT 7'h48
`define ADDR_WRC_DIAGS_WDIAG_TEMP 7'h4c
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