Commit 41e05c0a authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'proposed_master-ML-BTrain-dev' into proposed_master

parents cbdaa3df e7ba8d5f
This diff is collapsed.
......@@ -28,6 +28,7 @@ peripheral {
-----------------------------------------------------------------";
prefix = "wr_streamers";
hdl_entity = "wr_streamers_wb";
version= 1;
reg {
name = "Statistics status and ctrl register";
......
......@@ -3,7 +3,8 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Tue May 16 18:11:13 2017
-- Created : Tue Jun 20 08:53:54 2017
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
......@@ -68,6 +69,7 @@ package wr_streamers_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_wr_streamers_out_registers is record
ver_id_o : std_logic_vector(31 downto 0);
sscr1_rst_stats_o : std_logic;
sscr1_rst_seq_id_o : std_logic;
sscr1_snapshot_stats_o : std_logic;
......@@ -102,6 +104,7 @@ package wr_streamers_wbgen2_pkg is
end record;
constant c_wr_streamers_out_registers_init_value: t_wr_streamers_out_registers := (
ver_id_o => (others => '0'),
sscr1_rst_stats_o => '0',
sscr1_rst_seq_id_o => '0',
sscr1_snapshot_stats_o => '0',
......
......@@ -182,7 +182,7 @@ architecture rtl of xrx_streamer is
signal is_vlan : std_logic;
constant c_fixed_latency_zero : unsigned(27 downto 0) := (others => '0');
constant c_timestamper_delay : unsigned(27 downto 0) := to_unsigned(3, 28); -- cycles
constant c_timestamper_delay : unsigned(27 downto 0) := to_unsigned(12, 28); -- cycles
begin -- rtl
......
......@@ -3,7 +3,8 @@
---------------------------------------------------------------------------------------
-- File : wrc_diags_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
-- Created : Tue Apr 25 12:14:42 2017
-- Created : Tue Jun 20 09:59:03 2017
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
......@@ -70,10 +71,12 @@ package wrc_diags_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_wrc_diags_out_registers is record
ver_id_o : std_logic_vector(31 downto 0);
ctrl_data_snapshot_o : std_logic;
end record;
constant c_wrc_diags_out_registers_init_value: t_wrc_diags_out_registers := (
ver_id_o => (others => '0'),
ctrl_data_snapshot_o => '0'
);
function "or" (left, right: t_wrc_diags_in_registers) return t_wrc_diags_in_registers;
......
......@@ -3,7 +3,8 @@
---------------------------------------------------------------------------------------
-- File : wrc_diags_wb.vhd
-- Author : auto-generated by wbgen2 from wrc_diags_wb.wb
-- Created : Tue Apr 25 12:14:42 2017
-- Created : Tue Jun 20 09:59:03 2017
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
......@@ -37,26 +38,17 @@ end wrc_diags_wb;
architecture syn of wrc_diags_wb is
signal wrc_diags_ver_id_int : std_logic_vector(31 downto 0);
signal wrc_diags_ctrl_data_snapshot_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -65,6 +57,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
wrc_diags_ver_id_int <= "00000000000000000000000000000001";
wrc_diags_ctrl_data_snapshot_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
......@@ -79,6 +72,13 @@ begin
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
wrc_diags_ver_id_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= wrc_diags_ver_id_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
wrc_diags_ctrl_data_snapshot_int <= wrdata_reg(8);
end if;
......@@ -116,7 +116,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
when "00010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.wdiag_sstat_wr_mode_i;
......@@ -150,7 +150,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
when "00011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.wdiag_pstat_link_i;
......@@ -187,7 +187,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
when "00100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.wdiag_ptpstat_ptpstate_i;
......@@ -217,7 +217,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
when "00101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.wdiag_astat_aux_i;
......@@ -247,85 +247,85 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
when "00110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_txfcnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
when "00111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_rxfcnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
when "01000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_sec_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
when "01001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_sec_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
when "01010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_ns_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
when "01011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_mu_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
when "01100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_mu_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
when "01101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_dms_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
when "01110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_dms_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
when "01111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_asym_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
when "10000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_cko_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
when "10001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_setp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
when "10010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_ucnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
when "10011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.wdiag_temp_i;
......@@ -344,6 +344,8 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Version identifier
regs_o.ver_id_o <= wrc_diags_ver_id_int;
-- WR DIAG data valid
-- WR DIAG data snapshot
regs_o.ctrl_data_snapshot_o <= wrc_diags_ctrl_data_snapshot_int;
......
......@@ -5,6 +5,7 @@ peripheral {
description = "Diagnostics information accessible via WR";
prefix = "wrc_diags";
hdl_entity = "wrc_diags_wb";
version = 1;
reg {
name = "Ctrl";
......
`define ADDR_WR_STREAMERS_SSCR1 8'h0
`define WBGEN2_WR_STREAMERS_VERSION 32'h00000001
`define ADDR_WR_STREAMERS_VER 8'h0
`define WR_STREAMERS_VER_ID_OFFSET 0
`define WR_STREAMERS_VER_ID 32'hffffffff
`define ADDR_WR_STREAMERS_SSCR1 8'h4
`define WR_STREAMERS_SSCR1_RST_STATS_OFFSET 0
`define WR_STREAMERS_SSCR1_RST_STATS 32'h00000001
`define WR_STREAMERS_SSCR1_RST_SEQ_ID_OFFSET 1
......@@ -9,99 +13,99 @@
`define WR_STREAMERS_SSCR1_RX_LATENCY_ACC_OVERFLOW 32'h00000008
`define WR_STREAMERS_SSCR1_RST_TS_CYC_OFFSET 4
`define WR_STREAMERS_SSCR1_RST_TS_CYC 32'hfffffff0
`define ADDR_WR_STREAMERS_SSCR2 8'h4
`define ADDR_WR_STREAMERS_SSCR2 8'h8
`define WR_STREAMERS_SSCR2_RST_TS_TAI_LSB_OFFSET 0
`define WR_STREAMERS_SSCR2_RST_TS_TAI_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_SSCR3 8'h8
`define ADDR_WR_STREAMERS_SSCR3 8'hc
`define WR_STREAMERS_SSCR3_RST_TS_TAI_MSB_OFFSET 0
`define WR_STREAMERS_SSCR3_RST_TS_TAI_MSB 32'h000000ff
`define ADDR_WR_STREAMERS_RX_STAT0 8'hc
`define ADDR_WR_STREAMERS_RX_STAT0 8'h10
`define WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX_OFFSET 0
`define WR_STREAMERS_RX_STAT0_RX_LATENCY_MAX 32'h0fffffff
`define ADDR_WR_STREAMERS_RX_STAT1 8'h10
`define ADDR_WR_STREAMERS_RX_STAT1 8'h14
`define WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN_OFFSET 0
`define WR_STREAMERS_RX_STAT1_RX_LATENCY_MIN 32'h0fffffff
`define ADDR_WR_STREAMERS_TX_STAT2 8'h14
`define ADDR_WR_STREAMERS_TX_STAT2 8'h18
`define WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB_OFFSET 0
`define WR_STREAMERS_TX_STAT2_TX_SENT_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_STAT3 8'h18
`define ADDR_WR_STREAMERS_TX_STAT3 8'h1c
`define WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB_OFFSET 0
`define WR_STREAMERS_TX_STAT3_TX_SENT_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT4 8'h1c
`define ADDR_WR_STREAMERS_RX_STAT4 8'h20
`define WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT4_RX_RCVD_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT5 8'h20
`define ADDR_WR_STREAMERS_RX_STAT5 8'h24
`define WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT5_RX_RCVD_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT6 8'h24
`define ADDR_WR_STREAMERS_RX_STAT6 8'h28
`define WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT6_RX_LOSS_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT7 8'h28
`define ADDR_WR_STREAMERS_RX_STAT7 8'h2c
`define WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT7_RX_LOSS_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT8 8'h2c
`define ADDR_WR_STREAMERS_RX_STAT8 8'h30
`define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT8_RX_LOST_BLOCK_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT9 8'h30
`define ADDR_WR_STREAMERS_RX_STAT9 8'h34
`define WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT9_RX_LOST_BLOCK_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT10 8'h34
`define ADDR_WR_STREAMERS_RX_STAT10 8'h38
`define WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT10_RX_LATENCY_ACC_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT11 8'h38
`define ADDR_WR_STREAMERS_RX_STAT11 8'h3c
`define WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT11_RX_LATENCY_ACC_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT12 8'h3c
`define ADDR_WR_STREAMERS_RX_STAT12 8'h40
`define WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB_OFFSET 0
`define WR_STREAMERS_RX_STAT12_RX_LATENCY_ACC_CNT_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_STAT13 8'h40
`define ADDR_WR_STREAMERS_RX_STAT13 8'h44
`define WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB_OFFSET 0
`define WR_STREAMERS_RX_STAT13_RX_LATENCY_ACC_CNT_MSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG0 8'h44
`define ADDR_WR_STREAMERS_TX_CFG0 8'h48
`define WR_STREAMERS_TX_CFG0_ETHERTYPE_OFFSET 0
`define WR_STREAMERS_TX_CFG0_ETHERTYPE 32'h0000ffff
`define ADDR_WR_STREAMERS_TX_CFG1 8'h48
`define ADDR_WR_STREAMERS_TX_CFG1 8'h4c
`define WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_STREAMERS_TX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG2 8'h4c
`define ADDR_WR_STREAMERS_TX_CFG2 8'h50
`define WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_STREAMERS_TX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_TX_CFG3 8'h50
`define ADDR_WR_STREAMERS_TX_CFG3 8'h54
`define WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB_OFFSET 0
`define WR_STREAMERS_TX_CFG3_MAC_TARGET_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_TX_CFG4 8'h54
`define ADDR_WR_STREAMERS_TX_CFG4 8'h58
`define WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB_OFFSET 0
`define WR_STREAMERS_TX_CFG4_MAC_TARGET_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_TX_CFG5 8'h58
`define ADDR_WR_STREAMERS_TX_CFG5 8'h5c
`define WR_STREAMERS_TX_CFG5_QTAG_ENA_OFFSET 0
`define WR_STREAMERS_TX_CFG5_QTAG_ENA 32'h00000001
`define WR_STREAMERS_TX_CFG5_QTAG_VID_OFFSET 8
`define WR_STREAMERS_TX_CFG5_QTAG_VID 32'h000fff00
`define WR_STREAMERS_TX_CFG5_QTAG_PRIO_OFFSET 24
`define WR_STREAMERS_TX_CFG5_QTAG_PRIO 32'h07000000
`define ADDR_WR_STREAMERS_RX_CFG0 8'h5c
`define ADDR_WR_STREAMERS_RX_CFG0 8'h60
`define WR_STREAMERS_RX_CFG0_ETHERTYPE_OFFSET 0
`define WR_STREAMERS_RX_CFG0_ETHERTYPE 32'h0000ffff
`define WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST_OFFSET 16
`define WR_STREAMERS_RX_CFG0_ACCEPT_BROADCAST 32'h00010000
`define WR_STREAMERS_RX_CFG0_FILTER_REMOTE_OFFSET 17
`define WR_STREAMERS_RX_CFG0_FILTER_REMOTE 32'h00020000
`define ADDR_WR_STREAMERS_RX_CFG1 8'h60
`define ADDR_WR_STREAMERS_RX_CFG1 8'h64
`define WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB_OFFSET 0
`define WR_STREAMERS_RX_CFG1_MAC_LOCAL_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG2 8'h64
`define ADDR_WR_STREAMERS_RX_CFG2 8'h68
`define WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB_OFFSET 0
`define WR_STREAMERS_RX_CFG2_MAC_LOCAL_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG3 8'h68
`define ADDR_WR_STREAMERS_RX_CFG3 8'h6c
`define WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB_OFFSET 0
`define WR_STREAMERS_RX_CFG3_MAC_REMOTE_LSB 32'hffffffff
`define ADDR_WR_STREAMERS_RX_CFG4 8'h6c
`define ADDR_WR_STREAMERS_RX_CFG4 8'h70
`define WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB_OFFSET 0
`define WR_STREAMERS_RX_CFG4_MAC_REMOTE_MSB 32'h0000ffff
`define ADDR_WR_STREAMERS_RX_CFG5 8'h70
`define ADDR_WR_STREAMERS_RX_CFG5 8'h74
`define WR_STREAMERS_RX_CFG5_FIXED_LATENCY_OFFSET 0
`define WR_STREAMERS_RX_CFG5_FIXED_LATENCY 32'h0fffffff
`define ADDR_WR_STREAMERS_CFG 8'h74
`define ADDR_WR_STREAMERS_CFG 8'h78
`define WR_STREAMERS_CFG_OR_TX_ETHTYPE_OFFSET 0
`define WR_STREAMERS_CFG_OR_TX_ETHTYPE 32'h00000001
`define WR_STREAMERS_CFG_OR_TX_MAC_LOC_OFFSET 1
......@@ -122,12 +126,12 @@
`define WR_STREAMERS_CFG_OR_RX_FTR_REMOTE 32'h00100000
`define WR_STREAMERS_CFG_OR_RX_FIX_LAT_OFFSET 21
`define WR_STREAMERS_CFG_OR_RX_FIX_LAT 32'h00200000
`define ADDR_WR_STREAMERS_DBG_CTRL 8'h78
`define ADDR_WR_STREAMERS_DBG_CTRL 8'h7c
`define WR_STREAMERS_DBG_CTRL_MUX_OFFSET 0
`define WR_STREAMERS_DBG_CTRL_MUX 32'h00000001
`define WR_STREAMERS_DBG_CTRL_START_BYTE_OFFSET 8
`define WR_STREAMERS_DBG_CTRL_START_BYTE 32'h0000ff00
`define ADDR_WR_STREAMERS_DBG_DATA 8'h7c
`define ADDR_WR_STREAMERS_DUMMY 8'h80
`define ADDR_WR_STREAMERS_DBG_DATA 8'h80
`define ADDR_WR_STREAMERS_DUMMY 8'h84
`define WR_STREAMERS_DUMMY_DUMMY_OFFSET 0
`define WR_STREAMERS_DUMMY_DUMMY 32'hffffffff
`define ADDR_WRC_DIAGS_CTRL 7'h0
`define WBGEN2_WRC_DIAGS_VERSION 32'h00000001
`define ADDR_WRC_DIAGS_VER 7'h0
`define WRC_DIAGS_VER_ID_OFFSET 0
`define WRC_DIAGS_VER_ID 32'hffffffff
`define ADDR_WRC_DIAGS_CTRL 7'h4
`define WRC_DIAGS_CTRL_DATA_VALID_OFFSET 0
`define WRC_DIAGS_CTRL_DATA_VALID 32'h00000001
`define WRC_DIAGS_CTRL_DATA_SNAPSHOT_OFFSET 8
`define WRC_DIAGS_CTRL_DATA_SNAPSHOT 32'h00000100
`define ADDR_WRC_DIAGS_WDIAG_SSTAT 7'h4
`define ADDR_WRC_DIAGS_WDIAG_SSTAT 7'h8
`define WRC_DIAGS_WDIAG_SSTAT_WR_MODE_OFFSET 0
`define WRC_DIAGS_WDIAG_SSTAT_WR_MODE 32'h00000001
`define WRC_DIAGS_WDIAG_SSTAT_SERVOSTATE_OFFSET 8
`define WRC_DIAGS_WDIAG_SSTAT_SERVOSTATE 32'h00000f00
`define ADDR_WRC_DIAGS_WDIAG_PSTAT 7'h8
`define ADDR_WRC_DIAGS_WDIAG_PSTAT 7'hc
`define WRC_DIAGS_WDIAG_PSTAT_LINK_OFFSET 0
`define WRC_DIAGS_WDIAG_PSTAT_LINK 32'h00000001
`define WRC_DIAGS_WDIAG_PSTAT_LOCKED_OFFSET 1
`define WRC_DIAGS_WDIAG_PSTAT_LOCKED 32'h00000002
`define ADDR_WRC_DIAGS_WDIAG_PTPSTAT 7'hc
`define ADDR_WRC_DIAGS_WDIAG_PTPSTAT 7'h10
`define WRC_DIAGS_WDIAG_PTPSTAT_PTPSTATE_OFFSET 0
`define WRC_DIAGS_WDIAG_PTPSTAT_PTPSTATE 32'h000000ff
`define ADDR_WRC_DIAGS_WDIAG_ASTAT 7'h10
`define ADDR_WRC_DIAGS_WDIAG_ASTAT 7'h14
`define WRC_DIAGS_WDIAG_ASTAT_AUX_OFFSET 0
`define WRC_DIAGS_WDIAG_ASTAT_AUX 32'h000000ff
`define ADDR_WRC_DIAGS_WDIAG_TXFCNT 7'h14
`define ADDR_WRC_DIAGS_WDIAG_RXFCNT 7'h18
`define ADDR_WRC_DIAGS_WDIAG_SEC_MSB 7'h1c
`define ADDR_WRC_DIAGS_WDIAG_SEC_LSB 7'h20
`define ADDR_WRC_DIAGS_WDIAG_NS 7'h24
`define ADDR_WRC_DIAGS_WDIAG_MU_MSB 7'h28
`define ADDR_WRC_DIAGS_WDIAG_MU_LSB 7'h2c
`define ADDR_WRC_DIAGS_WDIAG_DMS_MSB 7'h30
`define ADDR_WRC_DIAGS_WDIAG_DMS_LSB 7'h34
`define ADDR_WRC_DIAGS_WDIAG_ASYM 7'h38
`define ADDR_WRC_DIAGS_WDIAG_CKO 7'h3c
`define ADDR_WRC_DIAGS_WDIAG_SETP 7'h40
`define ADDR_WRC_DIAGS_WDIAG_UCNT 7'h44
`define ADDR_WRC_DIAGS_WDIAG_TEMP 7'h48
`define ADDR_WRC_DIAGS_WDIAG_TXFCNT 7'h18
`define ADDR_WRC_DIAGS_WDIAG_RXFCNT 7'h1c
`define ADDR_WRC_DIAGS_WDIAG_SEC_MSB 7'h20
`define ADDR_WRC_DIAGS_WDIAG_SEC_LSB 7'h24
`define ADDR_WRC_DIAGS_WDIAG_NS 7'h28
`define ADDR_WRC_DIAGS_WDIAG_MU_MSB 7'h2c
`define ADDR_WRC_DIAGS_WDIAG_MU_LSB 7'h30
`define ADDR_WRC_DIAGS_WDIAG_DMS_MSB 7'h34
`define ADDR_WRC_DIAGS_WDIAG_DMS_LSB 7'h38
`define ADDR_WRC_DIAGS_WDIAG_ASYM 7'h3c
`define ADDR_WRC_DIAGS_WDIAG_CKO 7'h40
`define ADDR_WRC_DIAGS_WDIAG_SETP 7'h44
`define ADDR_WRC_DIAGS_WDIAG_UCNT 7'h48
`define ADDR_WRC_DIAGS_WDIAG_TEMP 7'h4c
......@@ -3,6 +3,8 @@
TB_DIRS=wr_minic
TB_DIRS+=wrc_core
TB_DIRS+=wr_streamers/streamers_multi_test
test_results_xml=test_results.xml
.PHONY: $(TB_DIRS)
......
interface IWishboneLink;
parameter g_data_width = 32;
parameter g_addr_width = 32;
wire [g_addr_width - 1 : 0] adr;
wire [g_data_width - 1 : 0] dat_o;
wire [g_data_width - 1 : 0] dat_i;
wire [(g_data_width/8)-1 : 0] sel;
wire ack;
wire stall;
wire err;
wire rty;
wire cyc;
wire stb;
wire we;
modport slave
(
output adr,
output dat_o,
input dat_i,
output sel,
output cyc,
output stb,
output we,
input ack,
input stall,
input err,
input rty
);
modport master
(
input adr,
input dat_o,
output dat_i,
input sel,
input cyc,
input stb,
input we,
output ack,
output stall,
output err,
output rty
);
endinterface // IWishboneLink
class CGENERATE_AND_SEND
// Generate a block of data words of random size, containing subsequent
// numbers
/////////////////////////////////////////////////////////////////////////////
task automatic generate_block(ref block_t blk);
int size = $dist_uniform(seed, g_block_size_min, g_block_size_max);
int i;
for(i = 0; i<size; i++)
begin
if (i == 0)
blk.first_wrd = tx_counter_val; // Copy first word
if (i == size-1)
blk.last_wrd = tx_counter_val; // Copy last word
blk.words.push_back(tx_counter_val++); //
if (i == 0 || i==size-1)
blk.wrd_cnt.push_back(i+1);// first or last words
else
blk.wrd_cnt.push_back(0); // All other words
end //for loop
endtask // generate_block
////////////////////////////////////////////////////////
task automatic generate_frame(ref streamer_frame_t frm);
int size = $dist_uniform(seed, g_frame_size_min, g_frame_size_max);
int i;
block_t blk;
for(i = 0; i<size; i++)
begin
blk.words = {};
blk.wrd_cnt = {};
generate_block(blk);
frm.blocks.push_back(blk);
end
endtask
// Sends out a data block (blk) by driving TX_(DVALID, DATA, LAST) lines
// of the TX streamer
/////////////////////////////////////////////////////////////////////////////
task automatic send_block(ref block_t blk);
int i = 0;
////$display("Sending block of %d words...", blk.words.data.size());
while(i < blk.words.size())
begin
if(tx_streamer_dreq) begin
// assert the TX_LAST line on the last word in the current block
tx_streamer_last <= (i == (blk.words.size() - 1)) ? 1 : 0;
tx_streamer_data <= blk.words[i];
//$display("Data to be sent is %d*****\n", tx_streamer_data);
tx_streamer_dvalid <= 1;
i++;
end else
tx_streamer_dvalid <= 0;
@(posedge clk);
end // while (i < blk.words.data.size())
tx_streamer_dvalid <= 0;
tx_streamer_last <= 0;
@(posedge clk);
endtask // send_block
///////////////////////////////////////////////////////////////////
task automatic send_frame(ref streamer_frame_t frm);
int i = 0;
while (i < frm.blocks.size()) begin
send_block(frm.blocks[i]);
i++;
end
endtask
endclass
\ No newline at end of file
//-----------------------------------------------------------------------------
// Title : Definitions for WR streamers testbench
// Project : White Rabbit Cores
// URL : http://www.ohwr.org/projects/wr-cores/wiki/WR_Streamers
//-----------------------------------------------------------------------------
// File : wr-streamers-tb-class.sv
// Author(s) : Denia Bouhired <denia.bouhired@cern.ch>
// Company : CERN (BE-CO-HT)
// Created : 2017-04-28
//-----------------------------------------------------------------------------
// Description:
//
// SystemVerilog package with all definitions, interfaces, etc. necessary
// for the wr streamers testbench.
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2017 CERN
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.gnu.org/licenses/lgpl-2.1.html
//
//-----------------------------------------------------------------------------
//`include "../../../sim/if_wb_link.svh"
class CWRFABRIC_LINK_CTRL;
int data_width, addr_width;
IWishboneLink in;
IWishboneLink out;
//Class constructor
function new ();
// this.out() = this.in();
// this.in.g_data_width = data_width;
// this.in.g_addr_width = addr_width;
// this.out.g_data_width = data_width;
// this.out.g_addr_width = addr_width;
endfunction //new
//
function corrupt_data ();
in();
out();
endfunction
function drop_frames ();
in();
out();
endfunction //drop_frames
function break_link ();
in();
out();
endfunction //break_link
endclass;
// Transmitter class
// class CWRSTREAMERS_TX extends CWRSTREAMERS;
// function
// endclass;
// Receiver class
// class CWRSTREAMERS_RX extends CWRSTREAMERS;
// endclass;
This diff is collapsed.
Wed May 03 16:18:04 W. Europe Daylight Time 2017
Trace back: invalid command name ""
while executing
"$tree expandeditems -worm"
(procedure "_resetTree" line 6)
invoked from within
"_resetTree $w"
(procedure "QObjects::sort" line 4)
invoked from within
"QObjects::sort .main_pane.objects 0 ascending"
("eval" body line 1)
invoked from within
"eval $itk_option(-sortcommand) $column $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::sort" body line 26)
invoked from within
"sort $sortIdx $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::_initializeSortColumn" body line 10)
invoked from within
"::.main_pane.objects.interior.cs.body.tree _initializeSortColumn"
(in namespace inscope "::vsimwidgets::Hierarchy" script line 1)
invoked from within
"namespace inscope ::vsimwidgets::Hierarchy {::.main_pane.objects.interior.cs.body.tree _initializeSortColumn}"
("after" script)
<2: ::tkerror {invalid command name ""}
<1: ::bgerror {invalid command name ""}
Wed May 24 15:41:46 W. Europe Daylight Time 2017
Trace back: invalid command name ""
while executing
"$tree expandeditems -worm"
(procedure "_resetTree" line 6)
invoked from within
"_resetTree $w"
(procedure "QObjects::sort" line 4)
invoked from within
"QObjects::sort .main_pane.objects 0 ascending"
("eval" body line 1)
invoked from within
"eval $itk_option(-sortcommand) $column $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::sort" body line 26)
invoked from within
"sort $sortIdx $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::_initializeSortColumn" body line 10)
invoked from within
"::.main_pane.objects.interior.cs.body.tree _initializeSortColumn"
(in namespace inscope "::vsimwidgets::Hierarchy" script line 1)
invoked from within
"namespace inscope ::vsimwidgets::Hierarchy {::.main_pane.objects.interior.cs.body.tree _initializeSortColumn}"
("after" script)
<2: ::tkerror {invalid command name ""}
<1: ::bgerror {invalid command name ""}
......@@ -109,7 +109,10 @@ module main;
#(
.g_data_width (g_record_size),
.g_tx_threshold (8),
.g_tx_timeout (512)
.g_tx_buffer_size(16),
.g_tx_max_words_per_frame(16),
.g_tx_timeout (512),
.g_simulation(1)
)
U_TX_Streamer
(
......@@ -141,7 +144,8 @@ module main;
rx_streamer
#(
.g_data_width (g_record_size)
.g_data_width (g_record_size),
.g_simulation(1)
)
U_RX_Streamer
(
......
......@@ -165,7 +165,10 @@ module main;
#(
.g_data_width (g_word_width),
.g_tx_threshold (8),
.g_tx_timeout (128)
.g_tx_buffer_size(16),
.g_tx_max_words_per_frame(16),
.g_tx_timeout (128),
.g_simulation(1)
)
U_TX_Streamer
(
......@@ -198,7 +201,8 @@ module main;
rx_streamer
#(
.g_data_width (g_word_width)
.g_data_width (g_word_width),
.g_simulation(1)
)
U_RX_Streamer
(
......
......@@ -7,5 +7,5 @@ set StdArithNoWarnings 1
do wave.do
run 10us
wave zoomfull
radix -hex
radix -dec
# make -f Makefile > /dev/null 2>&1
# Modelsim run script for continuous integration (with return code)
# execute: vsim -c -do "run_ci.do"
vsim -L unisim work.main -voptargs="+acc" -suppress 8684,8683
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
run 100us
run 100ms
wave zoomfull
radix -hex
coverage save coverage.ucdb
quit -code [coverage attribute -name TESTSTATUS -concise]
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/U_TX_Streamer/tx_flush_p1_i
add wave -noupdate /main/U_TX_Streamer/tx_last_p1_i
add wave -noupdate /main/U_TX_Streamer/tx_data_i
add wave -noupdate /main/U_TX_Streamer/tx_reset_seq_i
add wave -position end sim:/main/current_test
add wave -noupdate /main/U_TX_Streamer/tx_valid_i
add wave -noupdate /main/U_TX_Streamer/tx_data_i
add wave -noupdate /main/U_TX_Streamer/tx_last_p1_i
add wave -noupdate /main/U_TX_Streamer/tx_flush_p1_i
add wave -position end sim:/main/U_TX_Streamer/U_Wrapped_Streamer/fab_src.sof
add wave -position end sim:/main/U_TX_Streamer/U_Wrapped_Streamer/fab_src.eof
add wave -noupdate /main/U_TX_Streamer/tx_frame_p1_o
add wave -noupdate /main/U_TX_Streamer/tx_dreq_o
add wave -position 7 sim:/main/data_from_tx
add wave -position 8 sim:/main/data_to_rx
add wave -position 8 sim:/main/rx_streamer_lost_blks
add wave -position 9 sim:/main/rx_streamer_lost_frm
add wave -position 10 sim:/main/rx_streamer_lost_frm_cnt
add wave -noupdate /main/mac/adr
add wave -noupdate /main/mac/dat_o
add wave -noupdate /main/mac/dat_i
add wave -noupdate /main/mac/sel
add wave -noupdate /main/mac/ack
add wave -noupdate /main/mac/stall
add wave -noupdate /main/mac/err
add wave -noupdate /main/mac/rty
add wave -noupdate /main/mac/cyc
add wave -noupdate /main/mac/stb
add wave -noupdate /main/mac/we
#add wave -noupdate /main/U_TX_Streamer/tx_reset_seq_i
add wave -noupdate /main/U_RX_Streamer/rx_frame_p1_o
add wave -noupdate /main/U_RX_Streamer/rx_dreq_i
add wave -noupdate /main/U_RX_Streamer/rx_valid_o
add wave -noupdate /main/U_RX_Streamer/rx_data_o
add wave -noupdate /main/U_RX_Streamer/rx_first_p1_o
add wave -noupdate /main/U_RX_Streamer/rx_last_p1_o
add wave -noupdate /main/U_RX_Streamer/rx_data_o
add wave -noupdate /main/U_RX_Streamer/rx_valid_o
add wave -noupdate /main/U_RX_Streamer/rx_dreq_i
add wave -noupdate /main/U_RX_Streamer/rx_lost_p1_o
add wave -position end sim:/main/break_link
add wave -position end sim:/main/drop_frm
add wave -position end sim:/main/rx_streamer_lost_frm
add wave -position end sim:/main/rx_streamer_lost_frm_cnt
add wave -noupdate /main/U_RX_Streamer/rx_latency_o
add wave -noupdate /main/U_RX_Streamer/rx_latency_valid_o
add wave -position end sim:/main/rx_streamer_lost_blks
add wave -position end sim:/main/fab_data_from_tx
add wave -position end sim:/main/fab_data_to_rx
add wave -noupdate /main/mac/adr
#add wave -noupdate /main/mac/dat_o
#add wave -noupdate /main/mac/dat_i
#add wave -noupdate /main/mac/sel
#add wave -noupdate /main/mac/ack
#add wave -noupdate /main/mac/stall
add wave -noupdate /main/mac/err
add wave -noupdate /main/mac/rty
#add wave -noupdate /main/mac/cyc
#add wave -noupdate /main/mac/stb
#add wave -noupdate /main/mac/we
add wave -position end sim:/main/delay_link
add wave -position end sim:/main/tx_wb_ack
add wave -position end sim:/main/tx_wb_cyc
add wave -position end sim:/main/tx_wb_stall
add wave -position end sim:/main/tx_wb_stb
add wave -position end sim:/main/rx_wb_ack
add wave -position end sim:/main/rx_wb_cyc
add wave -position end sim:/main/tx_wb_ack
add wave -position end sim:/main/rx_wb_ack
add wave -position end sim:/main/rx_wb_stall
add wave -position end sim:/main/tx_wb_stall
add wave -position end sim:/main/tx_wb_stb
add wave -position end sim:/main/rx_wb_stb
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {867 ns} 0}
......
action= "simulation"
target= "xilinx"
syn_device="xc6slx45t"
sim_tool="modelsim"
top_module="main"
fetchto="../../../ip_cores"
vlog_opt="+incdir+../../../sim"
modules = { "local" : ["../../..",
"../../../modules/wr_streamers",
"../../../ip_cores/general-cores"]}
files = ["main.sv"]
interface IWishboneLink;
parameter g_data_width = 32;
parameter g_addr_width = 32;
wire [g_addr_width - 1 : 0] adr;
wire [g_data_width - 1 : 0] dat_o;
wire [g_data_width - 1 : 0] dat_i;
wire [(g_data_width/8)-1 : 0] sel;
wire ack;
wire stall;
wire err;
wire rty;
wire cyc;
wire stb;
wire we;
modport slave
(
output adr,
output dat_o,
input dat_i,
output sel,
output cyc,
output stb,
output we,
input ack,
input stall,
input err,
input rty
);
modport master
(
input adr,
input dat_o,
output dat_i,
input sel,
input cyc,
input stb,
input we,
output ack,
output stall,
output err,
output rty
);
endinterface // IWishboneLink
Wed May 03 16:18:04 W. Europe Daylight Time 2017
Trace back: invalid command name ""
while executing
"$tree expandeditems -worm"
(procedure "_resetTree" line 6)
invoked from within
"_resetTree $w"
(procedure "QObjects::sort" line 4)
invoked from within
"QObjects::sort .main_pane.objects 0 ascending"
("eval" body line 1)
invoked from within
"eval $itk_option(-sortcommand) $column $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::sort" body line 26)
invoked from within
"sort $sortIdx $dir"
(object "::.main_pane.objects.interior.cs.body.tree" method "::vsimwidgets::Hierarchy::_initializeSortColumn" body line 10)
invoked from within
"::.main_pane.objects.interior.cs.body.tree _initializeSortColumn"
(in namespace inscope "::vsimwidgets::Hierarchy" script line 1)
invoked from within
"namespace inscope ::vsimwidgets::Hierarchy {::.main_pane.objects.interior.cs.body.tree _initializeSortColumn}"
("after" script)
<2: ::tkerror {invalid command name ""}
<1: ::bgerror {invalid command name ""}
This diff is collapsed.
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