[eth_packet_sim] added information about port on which the packet should be sent (this is for sending from CPU/NIC)

In reverse dmtd mode, only first flip-flop should be sampling dmtd clk with
clk_in. That's done inside dmtd_with_deglitcher. Earlier the clocks were swapped
so the whole chain of flip-flops was clocked with clk_in which was wrong.

Conflicts:

	ip_cores/etherbone-core
	ip_cores/general-cores
	ip_cores/gn4124-core
	modules/wrc_core/wrcore_pkg.vhd
	modules/wrc_core/xwr_core.vhd
	syn/spec_1_1/wr_core_demo/Manifest.py
	syn/spec_1_1/wr_core_demo/spec_top_wrc.xise

The softpll_ng takes in a reset line from the sys clock domain.
It instantiates several dmtd_with_deglitcher FSMs which need reset.

The symptom of this bug is that on 3% of power-ups, some of the
deglitchers will not issue tags, because they power-on into an
undefined FSM state. This is caused by feeding the reset from a
different clock domain, leading to a race condition on release.

There was some code that probably used to solve this issue, whereby
the sys reset was synchronized to the clk_dmtd_i. However, the
softpll_ng instantiates multiple deglitchers, each in a different
domain and thus this single synchronizer chain can not work for all
of the deglitcher instances.

The fix is simple: synchronize the reset for each clock domain.

Under higher load of traffic SOF was being detected while main FSM was
not yet done with sending frame. That caused OOB FSM to reset and "tx
timestamp never became available" warnings in WR PTP Core software.

[EP/tx_head_proc] bugfix: we had a problem with handling the error from PCS - if it occured when already the next frame was being set (addr), the PCS got confused

Because the same module will be used in wrsw_nic for untagging frames.

switch-optimization: ep_rx_buffer: don't count bytes inside FIFO when there is no flow control (which is currently always the case)

count_o is connected to level_o but wr_endpoint doesn't use this information for flow control.

Conflicts:

	modules/wr_endpoint/endpoint_vectorized_top.vhd
	modules/wr_endpoint/ep_rx_path.vhd
	modules/wr_endpoint/ep_tx_path.vhd

improved test inj_gen mode configuration (can be changed separately from other config - different valid bit). This was convenient for software control implementation

corrected generation as it was sending 2 bytes more than in the set template (2-byte junk at the end)

corrected test-frame generation using pck_injection (dev/null before VLAN unit cause VLAN unit and injection unit use the same RAM)

bugfix: hanged when dreq=low from PCS at the last word (EOF from CRC) -> one of reaons: ugly bug in pack_fifo_content function

added abort of RTU request - in case of error in the input frame, receiving of frame is aborted, error status sent to SWcore, and the RTU request needs to be aborted as well, otherwise SWcore gets lost

bugfix: when frame corrupted in the header (or vlan unit droping frame cause frame is tagged and port is set to be access) the request to RTU was sent anyway... swcore was dropping frame, then receiving wrong RTU response... a mess. Now no rtu-req is done when frame corrupted in the header. still need to fix swcore->input block

changed the size of tx pcs fifo to an original (master, 20) - I stupiditly done it so big (40) that small frames would not get through