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White Rabbit core collection
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White Rabbit core collection
Commits
99dc19ae
Commit
99dc19ae
authored
Mar 25, 2015
by
Maciej Lipinski
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Plain Diff
[PSU] added signal from rt_subsystem to PSU to clear bit indicating announce msg reception
parent
c776cc38
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5 changed files
with
26 additions
and
6 deletions
+26
-6
spll_wb_slave.vhd
modules/wr_softpll_ng/spll_wb_slave.vhd
+7
-2
spll_wb_slave.wb
modules/wr_softpll_ng/spll_wb_slave.wb
+8
-3
spll_wbgen2_pkg.vhd
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
+5
-1
wr_softpll_ng.vhd
modules/wr_softpll_ng/wr_softpll_ng.vhd
+3
-0
xwr_softpll_ng.vhd
modules/wr_softpll_ng/xwr_softpll_ng.vhd
+3
-0
No files found.
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @
99dc19ae
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created :
Sun Mar 22 20:43:15
2015
-- Created :
Mon Mar 23 10:09:38
2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
...
...
@@ -113,6 +113,7 @@ begin
regs_o
.
dfr_spll_value_wr_o
<=
'0'
;
regs_o
.
dfr_spll_eos_wr_o
<=
'0'
;
spll_psu_holdover_int
<=
'0'
;
regs_o
.
psu_rx_holdover_msg_load_o
<=
'0'
;
spll_psu_selected_ref_id_int
<=
"00000"
;
eic_idr_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
...
...
@@ -136,6 +137,7 @@ begin
regs_o
.
dac_main_dac_sel_wr_o
<=
'0'
;
regs_o
.
dfr_spll_value_wr_o
<=
'0'
;
regs_o
.
dfr_spll_eos_wr_o
<=
'0'
;
regs_o
.
psu_rx_holdover_msg_load_o
<=
'0'
;
eic_idr_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
...
...
@@ -152,6 +154,7 @@ begin
regs_o
.
dac_main_dac_sel_wr_o
<=
'0'
;
regs_o
.
dfr_spll_value_wr_o
<=
'0'
;
regs_o
.
dfr_spll_eos_wr_o
<=
'0'
;
regs_o
.
psu_rx_holdover_msg_load_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
...
...
@@ -496,6 +499,7 @@ begin
when
"010101"
=>
if
(
wb_we_i
=
'1'
)
then
spll_psu_holdover_int
<=
wrdata_reg
(
0
);
regs_o
.
psu_rx_holdover_msg_load_o
<=
'1'
;
spll_psu_selected_ref_id_int
<=
wrdata_reg
(
12
downto
8
);
end
if
;
rddata_reg
(
0
)
<=
spll_psu_holdover_int
;
...
...
@@ -896,7 +900,8 @@ begin
-- States
-- Holdover State
regs_o
.
psu_holdover_o
<=
spll_psu_holdover_int
;
-- Received Announce with Holdover clock Class
-- Received Announce with Holdover clock Class, write 1 to clear
regs_o
.
psu_rx_holdover_msg_o
<=
wrdata_reg
(
1
);
-- Mask which indicates which reference input is used (i.e. active slave port)
regs_o
.
psu_selected_ref_id_o
<=
spll_psu_selected_ref_id_int
;
-- extra code for reg/fifo/mem: Interrupt disable register
...
...
modules/wr_softpll_ng/spll_wb_slave.wb
View file @
99dc19ae
...
...
@@ -412,11 +412,16 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "Received Announce with Holdover clock Class";
name = "Received Announce with Holdover clock Class, write 1 to clear";
description = "Informs about detection of Announce message that indactes the upstream clocks are in holdover:\
Read 0: no mesasage detected \
Read 1: detected announce with configured clockClass at configured active slave \
Write 1: clear flag.";
prefix = "RX_HOLDOVER_MSG";
load = LOAD_EXT;
type = BIT;
access_bus = READ_
ONLY
;
access_dev =
WRITE_ONLY
;
access_bus = READ_
WRITE
;
access_dev =
READ_WRITE
;
};
field {
name = "Mask which indicates which reference input is used (i.e. active slave port)";
...
...
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @
99dc19ae
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created :
Sun Mar 22 20:43:15
2015
-- Created :
Mon Mar 23 10:09:38
2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
...
...
@@ -114,6 +114,8 @@ package spll_wbgen2_pkg is
trr_wr_full_o
:
std_logic
;
trr_wr_empty_o
:
std_logic
;
psu_holdover_o
:
std_logic
;
psu_rx_holdover_msg_o
:
std_logic
;
psu_rx_holdover_msg_load_o
:
std_logic
;
psu_selected_ref_id_o
:
std_logic_vector
(
4
downto
0
);
end
record
;
...
...
@@ -149,6 +151,8 @@ package spll_wbgen2_pkg is
trr_wr_full_o
=>
'0'
,
trr_wr_empty_o
=>
'0'
,
psu_holdover_o
=>
'0'
,
psu_rx_holdover_msg_o
=>
'0'
,
psu_rx_holdover_msg_load_o
=>
'0'
,
psu_selected_ref_id_o
=>
(
others
=>
'0'
)
);
function
"or"
(
left
,
right
:
t_spll_in_registers
)
return
t_spll_in_registers
;
...
...
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @
99dc19ae
...
...
@@ -160,6 +160,7 @@ entity wr_softpll_ng is
-- 0: not in holdover (either locked or free-running)
holdover_on_o
:
out
std_logic
;
rx_holdover_msg_i
:
in
std_logic
;
rx_holdover_clr_o
:
out
std_logic
;
-- Debug FIFO readout interrupt
dbg_fifo_irq_o
:
out
std_logic
);
...
...
@@ -794,4 +795,6 @@ begin -- rtl
selected_ref_clk_o
<=
psu_selected_ref_mask
(
g_num_ref_inputs
-1
downto
0
);
regs_out
.
psu_rx_holdover_msg_i
<=
rx_holdover_msg_i
;
rx_holdover_clr_o
<=
'1'
when
(
regs_in
.
psu_rx_holdover_msg_o
=
'1'
and
regs_in
.
psu_rx_holdover_msg_load_o
=
'1'
)
else
'0'
;
end
rtl
;
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @
99dc19ae
...
...
@@ -128,6 +128,7 @@ entity xwr_softpll_ng is
selected_ref_clk_o
:
out
std_logic_vector
(
g_num_ref_inputs
-1
downto
0
);
holdover_on_o
:
out
std_logic
;
rx_holdover_msg_i
:
in
std_logic
;
rx_holdover_clr_o
:
out
std_logic
;
debug_o
:
out
std_logic_vector
(
5
downto
0
);
dbg_fifo_irq_o
:
out
std_logic
);
...
...
@@ -182,6 +183,7 @@ architecture wrapper of xwr_softpll_ng is
selected_ref_clk_o
:
out
std_logic_vector
(
g_num_ref_inputs
-1
downto
0
);
holdover_on_o
:
out
std_logic
;
rx_holdover_msg_i
:
in
std_logic
;
rx_holdover_clr_o
:
out
std_logic
;
dbg_fifo_irq_o
:
out
std_logic
);
end
component
;
...
...
@@ -233,6 +235,7 @@ begin -- behavioral
selected_ref_clk_o
=>
selected_ref_clk_o
,
holdover_on_o
=>
holdover_on_o
,
rx_holdover_msg_i
=>
rx_holdover_msg_i
,
rx_holdover_clr_o
=>
rx_holdover_clr_o
,
dbg_fifo_irq_o
=>
dbg_fifo_irq_o
);
slave_o
.
err
<=
'0'
;
...
...
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