added info about relation between set gap value and real IFG

a5e699c2 · Maciej Lipinski · Grzegorz Daniluk · e93e8cfa · a5e699c2
Commit a5e699c2 authored Jan 29, 2014 by Maciej Lipinski Committed by Grzegorz Daniluk Feb 04, 2014
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ep_tx_inject_ctrl.vhd modules/wr_endpoint/ep_tx_inject_ctrl.vhd +10 -0

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--- a/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
+++ b/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
@@ -97,6 +97,16 @@ architecture rtl of ep_tx_inject_ctrl is
  signal within_packet : std_logic;
  signal state         : t_state;

+  -- translation betwen if_gap_value and real IFG:
+  -- | ----------------------------------------- |
+  -- | if_gap_value | gap in words | gap in time |
+  -- |   0          |     7        |   112 ns    | disallowed 
+  -- | ......................................... |
+  -- |   5          |     12       |   192 ns    | minimal leagal
+  -- |   6          |     13       |   208 ns    | 
+  -- | ......................................... |
+  -- |   65536      |     65546    |   1.048ms   | maximum allowed due to register size (16 bits)
+  -- | ----------------------------------------- |
 begin  -- rtl

  p_detect_within : process(clk_sys_i)