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White Rabbit core collection
Commit c776cc38 authored by Maciej Lipinski's avatar Maciej Lipinski
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[PSU] added communication between SoftPLL and PTP support unit

parent 5ffad091
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Showing with 114 additions and 5 deletions
modules/wr_softpll_ng/spll_wb_slave.vhd
View file @ c776cc38
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Wed Oct 15 19:10:33 2014
-- Created : Sun Mar 22 20:43:15 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -55,6 +55,8 @@ signal spll_trr_in_int : std_logic_vector(31 downto 0);
signal spll_trr_out_int : std_logic_vector(31 downto 0);
signal spll_trr_rdreq_int : std_logic ;
signal spll_trr_rdreq_int_d0 : std_logic ;
signal spll_psu_holdover_int : std_logic ;
signal spll_psu_selected_ref_id_int : std_logic_vector(4 downto 0);
signal eic_idr_int : std_logic_vector(0 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(0 downto 0);
......@@ -110,6 +112,8 @@ begin
spll_deglitch_thr_int <= "0000000000000000";
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
spll_psu_holdover_int <= '0';
spll_psu_selected_ref_id_int <= "00000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -489,6 +493,41 @@ begin
rddata_reg(31 downto 0) <= regs_i.psr_states_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
if (wb_we_i = '1') then
spll_psu_holdover_int <= wrdata_reg(0);
spll_psu_selected_ref_id_int <= wrdata_reg(12 downto 8);
end if;
rddata_reg(0) <= spll_psu_holdover_int;
rddata_reg(1) <= regs_i.psu_rx_holdover_msg_i;
rddata_reg(12 downto 8) <= spll_psu_selected_ref_id_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
......@@ -855,6 +894,11 @@ begin
);
-- States
-- Holdover State
regs_o.psu_holdover_o <= spll_psu_holdover_int;
-- Received Announce with Holdover clock Class
-- Mask which indicates which reference input is used (i.e. active slave port)
regs_o.psu_selected_ref_id_o <= spll_psu_selected_ref_id_int;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(0) <= wrdata_reg(0);
-- extra code for reg/fifo/mem: Interrupt enable register
......
modules/wr_softpll_ng/spll_wb_slave.wb
View file @ c776cc38
......@@ -400,8 +400,36 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "PTP support unit (direct notification)";
prefix = "PSU";
field {
name = "Holdover State";
prefix = "HOLDOVER";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Received Announce with Holdover clock Class";
prefix = "RX_HOLDOVER_MSG";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Mask which indicates which reference input is used (i.e. active slave port)";
prefix = "SELECTED_REF_ID";
size = 5;
align = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
View file @ c776cc38
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Wed Oct 15 19:10:33 2014
-- Created : Sun Mar 22 20:43:15 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
......@@ -47,6 +47,7 @@ package spll_wbgen2_pkg is
trr_chan_id_i : std_logic_vector(6 downto 0);
trr_disc_i : std_logic;
psr_states_i : std_logic_vector(31 downto 0);
psu_rx_holdover_msg_i : std_logic;
end record;
constant c_spll_in_registers_init_value: t_spll_in_registers := (
......@@ -75,7 +76,8 @@ package spll_wbgen2_pkg is
trr_value_i => (others => '0'),
trr_chan_id_i => (others => '0'),
trr_disc_i => '0',
psr_states_i => (others => '0')
psr_states_i => (others => '0'),
psu_rx_holdover_msg_i => '0'
);
-- Output registers (WB slave -> user design)
......@@ -111,6 +113,8 @@ package spll_wbgen2_pkg is
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic;
psu_holdover_o : std_logic;
psu_selected_ref_id_o : std_logic_vector(4 downto 0);
end record;
constant c_spll_out_registers_init_value: t_spll_out_registers := (
......@@ -143,7 +147,9 @@ package spll_wbgen2_pkg is
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0',
trr_wr_empty_o => '0'
trr_wr_empty_o => '0',
psu_holdover_o => '0',
psu_selected_ref_id_o => (others => '0')
);
function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -200,6 +206,7 @@ tmp.trr_value_i := f_x_to_zero(left.trr_value_i) or f_x_to_zero(right.trr_value_
tmp.trr_chan_id_i := f_x_to_zero(left.trr_chan_id_i) or f_x_to_zero(right.trr_chan_id_i);
tmp.trr_disc_i := f_x_to_zero(left.trr_disc_i) or f_x_to_zero(right.trr_disc_i);
tmp.psr_states_i := f_x_to_zero(left.psr_states_i) or f_x_to_zero(right.psr_states_i);
tmp.psu_rx_holdover_msg_i := f_x_to_zero(left.psu_rx_holdover_msg_i) or f_x_to_zero(right.psu_rx_holdover_msg_i);
return tmp;
end function;
end package body;
modules/wr_softpll_ng/wr_softpll_ng.vhd
View file @ c776cc38
......@@ -44,6 +44,7 @@ use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.softpll_pkg.all;
use work.spll_wbgen2_pkg.all;
......@@ -150,7 +151,15 @@ entity wr_softpll_ng is
-- rx clock states (port up/down)
clk_rx_status_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) :=(others=>'0');
-- mask which indicates which reference is currently used (i.e. active port)
-- should be only one at at time
selected_ref_clk_o : out std_logic_vector(g_num_ref_inputs-1 downto 0);
-- 1: SoftPLL is in holdover mode
-- 0: not in holdover (either locked or free-running)
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
-- Debug FIFO readout interrupt
dbg_fifo_irq_o : out std_logic
);
......@@ -322,6 +331,7 @@ architecture rtl of wr_softpll_ng is
signal aligner_sample_valid, aligner_sample_ack : std_logic_vector(g_num_outputs downto 0);
signal aligner_sample_cref, aligner_sample_cin : t_aligner_sample_array;
signal psu_selected_ref_mask : std_logic_vector(31 downto 0);
begin -- rtl
U_Adapter : wb_slave_adapter
......@@ -779,5 +789,9 @@ begin -- rtl
wb_irq_o <= wb_irq_out;
holdover_on_o <= regs_in.psu_holdover_o;
psu_selected_ref_mask <= f_onehot_encode(regs_in.psu_selected_ref_id_o);
selected_ref_clk_o <= psu_selected_ref_mask(g_num_ref_inputs-1 downto 0);
regs_out.psu_rx_holdover_msg_i <= rx_holdover_msg_i;
end rtl;
modules/wr_softpll_ng/xwr_softpll_ng.vhd
View file @ c776cc38
......@@ -125,6 +125,9 @@ entity xwr_softpll_ng is
slave_o : out t_wishbone_slave_out;
-- rx clock states (port up/down)
clk_rx_status_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) :=(others=>'0');
selected_ref_clk_o : out std_logic_vector(g_num_ref_inputs-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic
);
......@@ -176,6 +179,9 @@ architecture wrapper of xwr_softpll_ng is
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
clk_rx_status_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) :=(others=>'0');
selected_ref_clk_o : out std_logic_vector(g_num_ref_inputs-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
dbg_fifo_irq_o : out std_logic);
end component;
......@@ -224,6 +230,9 @@ begin -- behavioral
wb_irq_o => slave_o.int,
debug_o => debug_o,
clk_rx_status_i => clk_rx_status_i,
selected_ref_clk_o => selected_ref_clk_o,
holdover_on_o => holdover_on_o,
rx_holdover_msg_i => rx_holdover_msg_i,
dbg_fifo_irq_o => dbg_fifo_irq_o);
slave_o.err <= '0';
......
sim/softpll_regs_ng.vh
View file @ c776cc38
......@@ -58,6 +58,13 @@
`define ADDR_SPLL_PSR 8'h50
`define SPLL_PSR_STATES_OFFSET 0
`define SPLL_PSR_STATES 32'hffffffff
`define ADDR_SPLL_PSU 8'h54
`define SPLL_PSU_HOLDOVER_OFFSET 0
`define SPLL_PSU_HOLDOVER 32'h00000001
`define SPLL_PSU_RX_HOLDOVER_MSG_OFFSET 1
`define SPLL_PSU_RX_HOLDOVER_MSG 32'h00000002
`define SPLL_PSU_SELECTED_REF_ID_OFFSET 8
`define SPLL_PSU_SELECTED_REF_ID 32'h00001f00
`define ADDR_SPLL_EIC_IDR 8'h60
`define SPLL_EIC_IDR_TAG_OFFSET 0
`define SPLL_EIC_IDR_TAG 32'h00000001
......
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