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VME64x core
Commit fab6cb51 authored by dpedrett's avatar dpedrett
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changes in some names, the vme64x features are the same as the precedent version 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@157 665b4545-5c6b-4c24-801b-41150b02b44b
parent 505f7f99
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hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ fab6cb51
...@@ -119,12 +119,12 @@ ...@@ -119,12 +119,12 @@
VME_BERR_o : out std_logic; VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic; VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic; VME_RETRY_n_o : out std_logic;
VME_LWORD_n_b_i : in std_logic; VME_LWORD_n_i : in std_logic;
VME_LWORD_n_b_o : out std_logic; VME_LWORD_n_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1); VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1); VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0); VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0); VME_DATA_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0); VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic; VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic; VME_IACK_n_i : in std_logic;
...@@ -152,12 +152,12 @@ ...@@ -152,12 +152,12 @@
STALL_i : in std_logic; STALL_i : in std_logic;
-- IRQ Generator -- IRQ Generator
INT_ack : out std_logic; -- when the IRQ controller acknowledges the Interrupt INT_ack_o : out std_logic; -- when the IRQ controller acknowledges the Interrupt
-- cycle it sends a pulse to the IRQ Generator -- cycle it sends a pulse to the IRQ Generator
IRQ_i : in std_logic; -- Interrupt request; the IRQ Generator sends a pulse to IRQ_i : in std_logic; -- Interrupt request; the IRQ Generator sends a pulse to
-- the IRQ Controller and it asserts one of the IRQ lines. -- the IRQ Controller and it asserts one of the IRQ lines.
-- Add by Davide for debug: -- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0) debug : out std_logic_vector(7 downto 0)
); );
end VME64xCore_Top; end VME64xCore_Top;
...@@ -253,7 +253,7 @@ begin ...@@ -253,7 +253,7 @@ begin
width => 32 width => 32
) )
port map ( port map (
reg_i => VME_DATA_b_i, reg_i => VME_DATA_i,
reg_o => VME_DATA_oversampled, reg_o => VME_DATA_oversampled,
clk_i => clk_i clk_i => clk_i
); );
...@@ -263,7 +263,7 @@ begin ...@@ -263,7 +263,7 @@ begin
width => 31 width => 31
) )
port map( port map(
reg_i => VME_ADDR_b_i, reg_i => VME_ADDR_i,
reg_o => VME_ADDR_oversampled, reg_o => VME_ADDR_oversampled,
clk_i => clk_i clk_i => clk_i
); );
...@@ -297,7 +297,7 @@ begin ...@@ -297,7 +297,7 @@ begin
LWORDinputSample : SigInputSample LWORDinputSample : SigInputSample
port map( port map(
sig_i => VME_LWORD_n_b_i, sig_i => VME_LWORD_n_i,
sig_o => VME_LWORD_n_oversampled, sig_o => VME_LWORD_n_oversampled,
clk_i => clk_i clk_i => clk_i
); );
...@@ -349,8 +349,8 @@ begin ...@@ -349,8 +349,8 @@ begin
-- VME -- VME
VME_RST_n_i => VME_RST_n_oversampled, VME_RST_n_i => VME_RST_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled, VME_AS_n_i => VME_AS_n_oversampled,
VME_LWORD_n_b_o => VME_LWORD_n_b_o, VME_LWORD_n_o => VME_LWORD_n_o,
VME_LWORD_n_b_i => VME_LWORD_n_oversampled, VME_LWORD_n_i => VME_LWORD_n_oversampled,
VME_RETRY_n_o => VME_RETRY_n_o, VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o, VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_WRITE_n_i => VME_WRITE_n_oversampled, VME_WRITE_n_i => VME_WRITE_n_oversampled,
...@@ -358,12 +358,12 @@ begin ...@@ -358,12 +358,12 @@ begin
VME_DTACK_n_o => s_VME_DTACK_VMEbus, VME_DTACK_n_o => s_VME_DTACK_VMEbus,
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus, VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_o => VME_BERR_o, VME_BERR_o => VME_BERR_o,
VME_ADDR_b_i => VME_ADDR_oversampled, VME_ADDR_i => VME_ADDR_oversampled,
VME_ADDR_b_o => VME_ADDR_b_o, VME_ADDR_o => VME_ADDR_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o, VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o, VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
VME_DATA_b_i => VME_DATA_oversampled, VME_DATA_i => VME_DATA_oversampled,
VME_DATA_b_o => s_VME_DATA_VMEbus, VME_DATA_o => s_VME_DATA_VMEbus,
VME_DATA_DIR_o => s_VME_DATA_DIR_VMEbus, VME_DATA_DIR_o => s_VME_DATA_DIR_VMEbus,
VME_DATA_OE_N_o => VME_DATA_OE_N_o, VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_AM_i => VME_AM_oversampled, VME_AM_i => VME_AM_oversampled,
...@@ -418,7 +418,7 @@ begin ...@@ -418,7 +418,7 @@ begin
numBytes => s_bytes, numBytes => s_bytes,
transfTime => s_time, transfTime => s_time,
-- debug -- debug
leds => leds leds => debug
); );
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
...@@ -426,10 +426,10 @@ begin ...@@ -426,10 +426,10 @@ begin
VME_IRQ_n_o <= not s_VME_IRQ_n_o; --The buffers will invert again the logic level VME_IRQ_n_o <= not s_VME_IRQ_n_o; --The buffers will invert again the logic level
WE_o <= not s_RW; WE_o <= not s_RW;
reset_o <= s_reset; reset_o <= s_reset;
INT_ack <= s_VME_DTACK_IRQ; INT_ack_o <= s_VME_DTACK_IRQ;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
--Multiplexer added on the output signal used by either VMEbus.vhd and the IRQ_controller.vhd --Multiplexer added on the output signal used by either VMEbus.vhd and the IRQ_controller.vhd
VME_DATA_b_o <= s_VME_DATA_VMEbus when VME_IACK_n_oversampled ='1' else VME_DATA_o <= s_VME_DATA_VMEbus when VME_IACK_n_oversampled ='1' else
s_VME_DATA_IRQ; s_VME_DATA_IRQ;
VME_DTACK_n_o <= s_VME_DTACK_VMEbus when VME_IACK_n_oversampled ='1' else VME_DTACK_n_o <= s_VME_DTACK_VMEbus when VME_IACK_n_oversampled ='1' else
s_VME_DTACK_IRQ; s_VME_DTACK_IRQ;
......
hdl/vme64x-core/rtl/VME_Access_Decode.vhd
View file @ fab6cb51
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
-- 2) AM = 0x2f -- 2) AM = 0x2f
-- 3) The initialization is finished (wait about 8800 ns after power-up or software reset) -- 3) The initialization is finished (wait about 8800 ns after power-up or software reset)
-- --
-- To Access the Wb bus we have 7 function; only one at time can be selected. If one of -- To Access the Wb bus we have 7 functions; only one at time can be selected. If one of
-- these functions is selected the CardSel signal is asserted (this is the responding Slave). -- these functions is selected the CardSel signal is asserted (this is the responding Slave).
-- To access the Wb bus we need to decode the AM and the address lines; so as shown in -- To access the Wb bus we need to decode the AM and the address lines; so as shown in
-- the block diagram the main component are two: VME_Funct_Match, VME_Am_Match. -- the block diagram the main component are two: VME_Funct_Match, VME_Am_Match.
......
hdl/vme64x-core/rtl/VME_Am_Match.vhd
View file @ fab6cb51
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
-- --
-- CERN,BE/CO-HT -- CERN,BE/CO-HT
--______________________________________________________________________________________ --______________________________________________________________________________________
-- File: VME_ Am_Match.vhd -- File: VME_Am_Match.vhd
--______________________________________________________________________________________ --______________________________________________________________________________________
-- Description: this component checks if the AM match. -- Description: this component checks if the AM match.
-- If it is the corrispondent AmMatch's bit is asserted. This condition is necessary but -- If it is the corrispondent AmMatch's bit is asserted. This condition is necessary but
......
hdl/vme64x-core/rtl/VME_CR_pack.vhd
View file @ fab6cb51
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
-- --
-- CERN,BE/CO-HT -- CERN,BE/CO-HT
--______________________________________________________________________________________ --______________________________________________________________________________________
-- File: VME_ CR_pack.vhd -- File: VME_CR_pack.vhd
--______________________________________________________________________________________ --______________________________________________________________________________________
-- Description: ROM memory (CR space) -- Description: ROM memory (CR space)
--______________________________________________________________________________ --______________________________________________________________________________
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ fab6cb51
...@@ -75,8 +75,8 @@ entity VME_bus is ...@@ -75,8 +75,8 @@ entity VME_bus is
-- VME signals -- VME signals
VME_RST_n_i : in std_logic; VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic; VME_AS_n_i : in std_logic;
VME_LWORD_n_b_o : out std_logic; VME_LWORD_n_o : out std_logic;
VME_LWORD_n_b_i : in std_logic; VME_LWORD_n_i : in std_logic;
VME_RETRY_n_o : out std_logic; VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic; VME_RETRY_OE_o : out std_logic;
VME_WRITE_n_i : in std_logic; VME_WRITE_n_i : in std_logic;
...@@ -84,12 +84,12 @@ entity VME_bus is ...@@ -84,12 +84,12 @@ entity VME_bus is
VME_DTACK_n_o : out std_logic; VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic; VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic; VME_BERR_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1); VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1); VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_ADDR_DIR_o : out std_logic; VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic; VME_ADDR_OE_N_o : out std_logic;
VME_DATA_b_i : in std_logic_vector(31 downto 0); VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0); VME_DATA_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic; VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic; VME_DATA_OE_N_o : out std_logic;
VME_AM_i : in std_logic_vector(5 downto 0); VME_AM_i : in std_logic_vector(5 downto 0);
...@@ -1117,8 +1117,8 @@ begin ...@@ -1117,8 +1117,8 @@ begin
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if s_dataToAddrBus = '1' then if s_dataToAddrBus = '1' then
VME_ADDR_b_o <= s_locDataSwap(63 downto 33); VME_ADDR_o <= s_locDataSwap(63 downto 33);
VME_LWORD_n_b_o <= s_locDataSwap(32); VME_LWORD_n_o <= s_locDataSwap(32);
end if; end if;
end if; end if;
end process; end process;
...@@ -1127,18 +1127,18 @@ begin ...@@ -1127,18 +1127,18 @@ begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if s_dataToAddrBus = '1' or s_dataToOutput = '1' then if s_dataToAddrBus = '1' or s_dataToOutput = '1' then
if s_addressingType = CR_CSR then if s_addressingType = CR_CSR then
VME_DATA_b_o <= std_logic_vector(s_locData(31 downto 0)); VME_DATA_o <= std_logic_vector(s_locData(31 downto 0));
else else
VME_DATA_b_o <= s_locDataSwap(31 downto 0); VME_DATA_o <= s_locDataSwap(31 downto 0);
end if; end if;
end if; end if;
end if; end if;
end process; end process;
---------------------ADDRESS_HANDLER_PROCESS------------------------| ---------------------ADDRESS_HANDLER_PROCESS------------------------|
--Local address & AM & 2e address phase latching --Local address & AM & 2e address phase latching
s_VMEaddrInput <= unsigned(VME_ADDR_b_i); s_VMEaddrInput <= unsigned(VME_ADDR_i);
s_LWORDinput <= VME_LWORD_n_b_i; s_LWORDinput <= VME_LWORD_n_i;
s_VMEdataInput <= unsigned(VME_DATA_b_i); s_VMEdataInput <= unsigned(VME_DATA_i);
p_addrLatching : process(clk_i) p_addrLatching : process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
...@@ -1315,10 +1315,10 @@ begin ...@@ -1315,10 +1315,10 @@ begin
--swap the data during read or write operation --swap the data during read or write operation
--sel= 000 --> No swap --sel= 000 --> No swap
--sel= 001 --> Swap Byte eg: 01234567 became 10325476 --sel= 001 --> Swap Byte eg: 01234567 become 10325476
--sel= 010 --> Swap Word eg: 01234567 became 23016745 --sel= 010 --> Swap Word eg: 01234567 become 23016745
--sel= 011 --> Swap Word+ Swap Byte eg: 01234567 became 32107654 --sel= 011 --> Swap Word+ Swap Byte eg: 01234567 become 32107654
--sel= 100 --> Swap DWord + Swap Word+ Swap Byte eg: 01234567 became 76543210 --sel= 100 --> Swap DWord + Swap Word+ Swap Byte eg: 01234567 become 76543210
swapper_write: VME_swapper port map( swapper_write: VME_swapper port map(
d_i => std_logic_vector(s_locDataIn), d_i => std_logic_vector(s_locDataIn),
sel => MBLT_Endian_i, sel => MBLT_Endian_i,
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ fab6cb51
...@@ -66,12 +66,12 @@ package vme64x_pack is ...@@ -66,12 +66,12 @@ package vme64x_pack is
constant c_CRAM_SIZE : integer := 1024; constant c_CRAM_SIZE : integer := 1024;
-- remember to set properly the "END_CRAM" register in the CR space -- remember to set properly the "END_CRAM" register in the CR space
-- WB addr width: -- WB addr width:
constant c_addr_width : integer := 64; constant c_addr_width : integer := 32;
-- --
constant DFS : integer := 2; -- for accessing at the ADEM's bit 2 constant DFS : integer := 2; -- for accessing at the ADEM's bit 2
constant XAM_MODE : integer := 0; -- for accessing at the ADER's bit 0 constant XAM_MODE : integer := 0; -- for accessing at the ADER's bit 0
-- Tclk in ns used to calculate the data transfer rate -- Tclk in ns used to calculate the data transfer rate
constant c_CLK_PERIOD : std_logic_vector(19 downto 0) := "00000000000000001010"; constant c_CLK_PERIOD : std_logic_vector(19 downto 0) := "00000000000000110010";
--AM table: --AM table:
constant c_A24_S_sup : std_logic_vector(5 downto 0) := "111101"; constant c_A24_S_sup : std_logic_vector(5 downto 0) := "111101";
constant c_A24_S : std_logic_vector(5 downto 0) := "111001"; constant c_A24_S : std_logic_vector(5 downto 0) := "111001";
...@@ -371,11 +371,11 @@ function f_log2_size (A : natural) return natural; ...@@ -371,11 +371,11 @@ function f_log2_size (A : natural) return natural;
clk_i : in std_logic; clk_i : in std_logic;
VME_RST_n_i : in std_logic; VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic; VME_AS_n_i : in std_logic;
VME_LWORD_n_b_i : in std_logic; VME_LWORD_n_i : in std_logic;
VME_WRITE_n_i : in std_logic; VME_WRITE_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0); VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_ADDR_b_i : in std_logic_vector(31 downto 1); VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0); VME_DATA_i : in std_logic_vector(31 downto 0);
VME_AM_i : in std_logic_vector(5 downto 0); VME_AM_i : in std_logic_vector(5 downto 0);
VME_IACK_n_i : in std_logic; VME_IACK_n_i : in std_logic;
memAckWB_i : in std_logic; memAckWB_i : in std_logic;
...@@ -402,16 +402,16 @@ function f_log2_size (A : natural) return natural; ...@@ -402,16 +402,16 @@ function f_log2_size (A : natural) return natural;
BAR_i : in std_logic_vector(4 downto 0); BAR_i : in std_logic_vector(4 downto 0);
transfer_done_i : in std_logic; transfer_done_i : in std_logic;
reset_o : out std_logic; reset_o : out std_logic;
VME_LWORD_n_b_o : out std_logic; VME_LWORD_n_o : out std_logic;
VME_RETRY_n_o : out std_logic; VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic; VME_RETRY_OE_o : out std_logic;
VME_DTACK_n_o : out std_logic; VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic; VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic; VME_BERR_o : out std_logic;
VME_ADDR_b_o : out std_logic_vector(31 downto 1); VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_ADDR_DIR_o : out std_logic; VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic; VME_ADDR_OE_N_o : out std_logic;
VME_DATA_b_o : out std_logic_vector(31 downto 0); VME_DATA_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic; VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic; VME_DATA_OE_N_o : out std_logic;
memReq_o : out std_logic; memReq_o : out std_logic;
......
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