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VME64x core
Commit d681e2a3 authored by Tristan Gingold's avatar Tristan Gingold
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Doc improved.

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documentation/specifications/VME64x_v2_specs.txt
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...@@ -3,13 +3,12 @@ VME64x Core specifications ...@@ -3,13 +3,12 @@ VME64x Core specifications
This core implements a VME64x slave - WB master bridge. It provides a complete This core implements a VME64x slave - WB master bridge. It provides a complete
and user extendable CR/CSR space, and forward to a wishbone slave VME and user extendable CR/CSR space, and forward to a wishbone slave VME
transfers. transfers. On the WB side, the addresses are rebased from 0.
Features Features
-------- --------
* interrupts: 1 with timeout * interrupts: 1 with timeout
* endianness: disabled by default
* A disable ADEM (set to 0) results in an unimplemented ADER, to reduce gate * A disable ADEM (set to 0) results in an unimplemented ADER, to reduce gate
usage. usage.
* CSR Reset bit is handled as a pulse (will reset on the next write). * CSR Reset bit is handled as a pulse (will reset on the next write).
...@@ -25,6 +24,7 @@ Changes ...@@ -25,6 +24,7 @@ Changes
* No retry * No retry
* No endianess convertion * No endianess convertion
* WB data bus is 32 bit * WB data bus is 32 bit
* Internal component declarations removed.
* Port function_o to be removed. * Port function_o to be removed.
VME interface VME interface
...@@ -76,9 +76,16 @@ WB interface (datasheet) ...@@ -76,9 +76,16 @@ WB interface (datasheet)
Generics Generics
-------- --------
The generics define values for many CR registers, and the clock period (needed
to follow the VME timing specifications). See generic declarations for
details.
Ports Ports
----- -----
In addition to reset and clock, the ports are used for VME and WB signals,
to connect a user defined CSR or CR memory, interrupts from the WB slave,
VME irq level and vector. See port declaration for details.
TODO: TODO:
----- -----
......
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ d681e2a3
...@@ -195,7 +195,7 @@ entity VME64xCore_Top is ...@@ -195,7 +195,7 @@ entity VME64xCore_Top is
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
rst_n_o : out std_logic; rst_n_o : out std_logic; -- To wishbone
-- VME -- VME
VME_AS_n_i : in std_logic; VME_AS_n_i : in std_logic;
......
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