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VME64x core
Commit ca638b8e authored by dpedrett's avatar dpedrett
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svec top level and testbench files updated 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@193 665b4545-5c6b-4c24-801b-41150b02b44b
parent dcc45631
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Showing with 209 additions and 192 deletions
hdl/boards/svec/rtl/IRQ_Generator_Top.vhd
View file @ ca638b8e
......@@ -40,8 +40,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -64,8 +64,8 @@
-- Entity declaration
--===========================================================================
entity IRQ_Generator_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port ( -- IRQ_Generator
clk_i : in std_logic;
......@@ -75,15 +75,15 @@ generic(g_width : integer := c_width;
-- wb slave side
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0);
adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector (g_width - 1 downto 0);
dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0)
dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0)
);
end IRQ_Generator_Top;
--===========================================================================
......@@ -99,7 +99,7 @@ signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_data : std_logic_vector(31 downto 0);
signal s_data_f : std_logic_vector(31 downto 0);
signal s_data_o : std_logic_vector(g_width - 1 downto 0);
signal s_data_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal s_IntCount_sel : std_logic;
signal s_Freq_sel : std_logic;
signal s_wea : std_logic;
......@@ -141,7 +141,7 @@ s_en_Freq <= '1' when (s_Freq_sel = '1' and s_wea = '1') else '0';
-- the WB data bus is 32 or 64 bit width, so the following processes have been
-- added:
gen64 : if (g_width = 64) generate
gen64 : if (g_wb_data_width = 64) generate
s_data <= dat_i(63 downto 32);
s_data_f <= dat_i(31 downto 0);
s_data_o <= s_INT_COUNT & s_FREQ;
......@@ -151,7 +151,7 @@ gen64 : if (g_width = 64) generate
'0';
end generate gen64;
gen32 : if (g_width = 32) generate
gen32 : if (g_wb_data_width = 32) generate
s_data <= dat_i;
s_data_f <= dat_i;
s_data_o <= s_INT_COUNT when s_IntCount_sel = '1' else
......
hdl/boards/svec/rtl/IRQ_generator.vhd
View file @ ca638b8e
......@@ -57,8 +57,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/boards/svec/rtl/TOP_LEVEL.vhd
View file @ ca638b8e
......@@ -60,8 +60,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -85,18 +85,25 @@ use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
use work.vme64x_pack.all;
use work.genram_pkg.all;
use work.VME_CR_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity TOP_LEVEL is
generic(--WB data width:
g_width : integer := 64; --c_width;
generic(
g_clock : integer := 10;
--WB data width:
g_wb_data_width : integer := 64; --c_width;
-- WB addr width:
g_addr_width : integer := 11; --c_addr_width;
g_wb_addr_width : integer := 11; --c_addr_width;
--CRAM size in the CR/CSR space (bytes):
g_CRAM_SIZE : integer := 1024; --c_CRAM_SIZE;
g_cram_size : integer := 1024; --c_CRAM_SIZE;
--My WB slave memory:
g_WB_memory_size : integer := 1024 -- c_SIZE
g_WB_memory_size : integer := 1024; -- c_SIZE
g_BoardID : integer := 408; -- 0x00000198
g_ManufacturerID : integer := 524336; -- 0x080030
g_RevisionID : integer := 1; -- 0x00000001
g_ProgramID : integer := 90 -- 0x0000005a
);
port(
clk_i : in std_logic;
......@@ -136,9 +143,15 @@ end TOP_LEVEL;
architecture Behavioral of TOP_LEVEL is
component VME64xCore_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width;
g_CRAM_SIZE : integer := c_CRAM_SIZE
generic(
g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96 -- 0x00000060
);
port(
-- VME signals:
......@@ -169,15 +182,15 @@ component VME64xCore_Top is
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WB signals
DAT_i : in std_logic_vector(g_width - 1 downto 0);
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
ERR_i : in std_logic;
RTY_i : in std_logic;
ACK_i : in std_logic;
STALL_i : in std_logic;
DAT_o : out std_logic_vector(g_width - 1 downto 0);
ADR_o : out std_logic_vector(g_addr_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
SEL_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
WE_o : out std_logic;
-- IRQ Generator
......@@ -205,8 +218,9 @@ component xwb_ram is
end component xwb_ram;
component WB_Bridge is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
generic(
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
......@@ -214,50 +228,50 @@ generic(g_width : integer := c_width;
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_addr_width - 1 downto 0);
dat_i : in std_logic_vector(g_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_width) - 1 downto 0);
adr_i : in std_logic_vector(g_wb_addr_width - 1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector(g_width - 1 downto 0);
m_dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_width - 1 downto 0);
dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector(g_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector(g_width - 1 downto 0);
m_sel_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
m_adr_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
m_sel_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
m_we_o : out std_logic
);
end component WB_Bridge;
signal WbDat_i : std_logic_vector(g_width - 1 downto 0);
signal WbDat_o : std_logic_vector(g_width - 1 downto 0);
signal WbAdr_o : std_logic_vector(g_addr_width - 1 downto 0);
signal WbDat_i : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbDat_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbAdr_o : std_logic_vector(g_wb_addr_width - 1 downto 0);
signal WbCyc_o : std_logic;
signal WbErr_i : std_logic;
signal WbRty_i : std_logic;
signal WbSel_o : std_logic_vector(f_div8(g_width) - 1 downto 0);
signal WbSel_o : std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
signal WbStb_o : std_logic;
signal WbAck_i : std_logic;
signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal WbMemDat_i : std_logic_vector(g_width - 1 downto 0);
signal WbMemDat_o : std_logic_vector(g_width - 1 downto 0);
signal WbMemAdr_i : std_logic_vector(g_addr_width - 1 downto 0);
signal WbMemDat_i : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbMemDat_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbMemAdr_i : std_logic_vector(g_wb_addr_width - 1 downto 0);
signal WbMemCyc_i : std_logic;
signal WbMemErr_o : std_logic;
signal WbMemRty_o : std_logic;
signal WbMemSel_i : std_logic_vector(f_div8(g_width) - 1 downto 0);
signal WbMemSel_i : std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
signal WbMemStb_i : std_logic;
signal WbMemAck_o : std_logic;
signal WbMemWe_i : std_logic;
......@@ -284,8 +298,14 @@ begin
Inst_VME64xCore_Top: VME64xCore_Top
generic map(
g_width => g_width,
g_addr_width => g_addr_width
g_clock => g_clock,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_cram_size => g_cram_size,
g_BoardID => g_BoardID,
g_ManufacturerID => g_ManufacturerID,
g_RevisionID => g_RevisionID,
g_ProgramID => g_ProgramID
)
port map(
-- VME
......@@ -360,8 +380,8 @@ Inst_xwb_ram: xwb_ram
Inst_WB_Bridge: WB_Bridge
generic map(
g_width => g_width,
g_addr_width => g_addr_width
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
)
port map(
clk_i => clk_in,
......
hdl/boards/svec/rtl/WB_Bridge.vhd
View file @ ca638b8e
......@@ -20,8 +20,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -45,8 +45,8 @@ use work.vme64x_pack.all;
-- Entity declaration
--===========================================================================
entity WB_Bridge is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
Port ( clk_i : in std_logic;
rst_i : in std_logic;
......@@ -54,26 +54,26 @@ generic(g_width : integer := c_width;
Int_Req_o : out std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0);
dat_i : in std_logic_vector (g_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0);
adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0);
dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector (g_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector (g_width - 1 downto 0);
m_sel_o : out std_logic_vector (f_div8(g_width) - 1 downto 0);
m_adr_o : out std_logic_vector (g_wb_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_sel_o : out std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
m_we_o : out std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector (g_width - 1 downto 0));
m_dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0));
end WB_Bridge;
--===========================================================================
-- Architecture declaration
......@@ -89,11 +89,11 @@ signal s_ack_gen : std_logic;
signal s_err_gen : std_logic;
signal s_rty_gen : std_logic;
signal s_stall_gen : std_logic;
signal s_data_o_gen : std_logic_vector(g_width - 1 downto 0);
signal s_data_o_gen : std_logic_vector(g_wb_data_width - 1 downto 0);
component IRQ_Generator_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
......@@ -101,16 +101,16 @@ signal s_data_o_gen : std_logic_vector(g_width - 1 downto 0);
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_addr_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_width) - 1 downto 0);
adr_i : in std_logic_vector(g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector(g_width - 1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_width - 1 downto 0)
dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0)
);
end component IRQ_Generator_Top;
--===========================================================================
......@@ -121,11 +121,11 @@ begin
-- check if the IRQ Generator is addressed (0x00 or 0x04).
-- if not s_WbAppl is '1' and the component work as a bridge
-- between the vme64x core and the Wb Application
genIRQGen64 : if (g_width = 64) generate
genIRQGen64 : if (g_wb_data_width = 64) generate
s_IRQGen <= '1' when (unsigned(adr_i) = 0) else '0';
end generate genIRQGen64;
genIRQGen32 : if (g_width = 32) generate
genIRQGen32 : if (g_wb_data_width = 32) generate
s_IRQGen <= '1' when unsigned(adr_i) = 0 or
unsigned(adr_i) = 1 else '0';
end generate genIRQGen32;
......@@ -154,8 +154,8 @@ m_sel_o <= sel_i;
m_we_o <= we_i;
----------------------------------------------------------------------
Inst_IRQ_Generator_Top: IRQ_Generator_Top
generic map(g_width => g_width,
g_addr_width => g_addr_width
generic map(g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
)
port map(
clk_i => clk_i,
......
hdl/boards/svec/rtl/ram_8bits.vhd
View file @ ca638b8e
......@@ -9,8 +9,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/boards/svec/rtl/spram.vhd
View file @ ca638b8e
......@@ -11,8 +11,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/boards/svec/rtl/xwb_ram.vhd
View file @ ca638b8e
......@@ -38,8 +38,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/boards/svec/sim/testbench/VME64x_SIM_Package.vhd
View file @ ca638b8e
......@@ -9,7 +9,7 @@
--
-- Company : CERN
--
-- Description : VME64x procedures for test the VME64x Slave
-- Description : VME64x procedures for test the VME64x core
library IEEE;
library std;
......
hdl/boards/svec/sim/testbench/VME64x_TB.vhd
View file @ ca638b8e
......@@ -24,34 +24,35 @@ ARCHITECTURE behavior OF VME64x_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TOP_LEVEL
PORT(
clk_i : IN std_logic;
VME_AS_n_i : IN std_logic;
VME_RST_n_i : IN std_logic;
VME_WRITE_n_i : IN std_logic;
VME_AM_i : IN std_logic_vector(5 downto 0);
VME_DS_n_i : IN std_logic_vector(1 downto 0);
VME_GA_i : IN std_logic_vector(5 downto 0);
VME_BERR_o : OUT std_logic;
VME_DTACK_n_o : OUT std_logic;
VME_RETRY_n_o : OUT std_logic;
VME_RETRY_OE_o : OUT std_logic;
VME_LWORD_n_b : INOUT std_logic;
VME_ADDR_b : INOUT std_logic_vector(31 downto 1);
VME_DATA_b : INOUT std_logic_vector(31 downto 0);
VME_IRQ_n_o : OUT std_logic_vector(6 downto 0);
VME_IACK_n_i : IN std_logic;
VME_IACKIN_n_i : IN std_logic;
VME_IACKOUT_n_o : OUT std_logic;
VME_DTACK_OE_o : OUT std_logic;
VME_DATA_DIR_o : OUT std_logic;
VME_DATA_OE_N_o : OUT std_logic;
VME_ADDR_DIR_o : OUT std_logic;
VME_ADDR_OE_N_o : OUT std_logic;
Reset : IN std_logic
);
END COMPONENT;
COMPONENT TOP_LEVEL
PORT(
clk_i : IN std_logic;
Reset : IN std_logic;
VME_AS_n_i : IN std_logic;
VME_RST_n_i : IN std_logic;
VME_WRITE_n_i : IN std_logic;
VME_AM_i : IN std_logic_vector(5 downto 0);
VME_DS_n_i : IN std_logic_vector(1 downto 0);
VME_GA_i : IN std_logic_vector(5 downto 0);
VME_IACKIN_n_i : IN std_logic;
VME_IACK_n_i : IN std_logic;
VME_LWORD_n_b : INOUT std_logic;
VME_ADDR_b : INOUT std_logic_vector(31 downto 1);
VME_DATA_b : INOUT std_logic_vector(31 downto 0);
VME_BERR_o : OUT std_logic;
VME_DTACK_n_o : OUT std_logic;
VME_RETRY_n_o : OUT std_logic;
VME_IRQ_n_o : OUT std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : OUT std_logic;
VME_RETRY_OE_o : OUT std_logic;
VME_DTACK_OE_o : OUT std_logic;
VME_DATA_DIR_o : OUT std_logic;
VME_DATA_OE_N_o : OUT std_logic;
VME_ADDR_DIR_o : OUT std_logic;
VME_ADDR_OE_N_o : OUT std_logic;
leds : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
......@@ -111,34 +112,35 @@ ARCHITECTURE behavior OF VME64x_TB IS
constant clk_i_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TOP_LEVEL PORT MAP(
clk_i => clk_i,
Reset => Reset,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_LWORD_n_b => VME_LWORD_n_b,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_IACK_n_i => VME_IACK_n_i,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
leds => open
);
-- Instantiate the Unit Under Test (UUT)
uut: TOP_LEVEL PORT MAP (
clk_i => clk_i,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b => VME_LWORD_n_b,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
Reset => Reset
);
VME_IACKIN_n_i <= VME64xBus_out.Vme64xIACKIN;
VME_IACK_n_i <= VME64xBus_out.Vme64xIACK;
......
hdl/boards/svec/sim/testbench/wave1.do
View file @ ca638b8e
......@@ -17,7 +17,6 @@ add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_RETRY_n_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_LWORD_n_b
add wave -noupdate -expand -group VME_TOP -radix hexadecimal /vme64x_tb/uut/VME_ADDR_b
add wave -noupdate -expand -group VME_TOP -radix hexadecimal /vme64x_tb/uut/VME_DATA_b
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_BBSY_n_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_IRQ_n_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_IACKIN_n_i
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_IACKOUT_n_o
......@@ -29,9 +28,6 @@ add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_DATA_OE_N_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_ADDR_DIR_o
add wave -noupdate -expand -group VME_TOP /vme64x_tb/uut/VME_ADDR_OE_N_o
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/clk_i
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/s_reset
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/s_mainFSMreset
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/s_decode
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/ModuleEnable
add wave -noupdate -group DecodeAccess /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/InitInProgress
add wave -noupdate -group DecodeAccess -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Access_Decode/Addr
......@@ -87,7 +83,6 @@ add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/WbSel_o
add wave -noupdate -group VME_WB /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/Inst_Wb_master/RW_o
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/clk_i
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/reset
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_IACKIN_n_i
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_AS_n_i
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_DS_n_i
......@@ -100,7 +95,6 @@ add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_IACKOUT_n_o
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_DTACK_n_o
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/VME_DATA_o
add wave -noupdate -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_IRQ_Controller/currs
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_cyc_o
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_stb_o
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_adr_o
......@@ -112,6 +106,7 @@ add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_stall_i
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_rty_i
add wave -noupdate -expand -group WB_Bridge_out /vme64x_tb/uut/Inst_WB_Bridge/m_dat_i
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_VME_bus/s_VMEaddrInput
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8963596 ps} 0}
configure wave -namecolwidth 150
......@@ -128,4 +123,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {34872407 ps} {35359347 ps}
WaveRestoreZoom {7948848 ps} {10676982 ps}
hdl/boards/svec/syn/VME64x_SVECTest.xise
View file @ ca638b8e
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