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VME64x core
Commit c800dc8d authored by palvarez's avatar palvarez
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added some signals to chipscope 


git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@92 665b4545-5c6b-4c24-801b-41150b02b44b
parent 84b19510
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Showing with 95 additions and 30 deletions
HDL/VFC_ISE/VME64e_VFC.gise
View file @ c800dc8d
......@@ -326,7 +326,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1309177111" xil_pn:in_ck="1991227451224517426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5973292016675018579" xil_pn:start_ts="1309177095">
<transform xil_pn:end_ts="1309270151" xil_pn:in_ck="1991227451224517426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5973292016675018579" xil_pn:start_ts="1309270031">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -338,7 +338,7 @@
<outfile xil_pn:name="vme64xcore_top_reg_cs.ngc"/>
<outfile xil_pn:name="vme64xcore_top_reg_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1309177242" xil_pn:in_ck="-8441102077107081157" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1824173063049107586" xil_pn:start_ts="1309177111">
<transform xil_pn:end_ts="1309270268" xil_pn:in_ck="-8441102077107081157" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1824173063049107586" xil_pn:start_ts="1309270151">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -351,7 +351,7 @@
<outfile xil_pn:name="vme64xcore_top_reg_summary.xml"/>
<outfile xil_pn:name="vme64xcore_top_reg_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1309177348" xil_pn:in_ck="3353801450926630214" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="2881300017542290041" xil_pn:start_ts="1309177242">
<transform xil_pn:end_ts="1309270390" xil_pn:in_ck="3353801450926630214" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="2881300017542290041" xil_pn:start_ts="1309270268">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -365,7 +365,7 @@
<outfile xil_pn:name="vme64xcore_top_reg_pad.txt"/>
<outfile xil_pn:name="vme64xcore_top_reg_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1309177394" xil_pn:in_ck="-6139244621610154419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="2321585675605421658" xil_pn:start_ts="1309177348">
<transform xil_pn:end_ts="1309270443" xil_pn:in_ck="-6139244621610154419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="2321585675605421658" xil_pn:start_ts="1309270390">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -391,6 +391,8 @@
<transform xil_pn:end_ts="1309177396" xil_pn:in_ck="-94636564203146769" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1309177394">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="vme64xcore_top_reg.mcs"/>
<outfile xil_pn:name="vme64xcore_top_reg.prm"/>
</transform>
......@@ -405,7 +407,7 @@
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1309177348" xil_pn:in_ck="-6179112853177871454" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="5478904096812716945" xil_pn:start_ts="1309177331">
<transform xil_pn:end_ts="1309270390" xil_pn:in_ck="-6179112853177871454" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="5478904096812716945" xil_pn:start_ts="1309270371">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
HDL/VFC_ISE/VME64e_VFC.xise
View file @ c800dc8d
......@@ -445,8 +445,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/vme64xcore_top_ddr3/Uddr3_ctrl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ddr3_ctrl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/vme64xcore_top_tb/stimulGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.sim_vme64master" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.vme64xcore_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -470,7 +470,7 @@
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ddr3_ctrl" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.sim_vme64master" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.vme64xcore_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
HDL/VFC_ISE/VMEScope.cdc
View file @ c800dc8d
#ChipScope Core Inserter Project File Version 3.0
#Wed Jun 22 17:15:57 CEST 2011
#Tue Jun 28 16:07:04 CEST 2011
Project.device.designInputFile=/ohr/vme64x-core/trunk/HDL/VFC_ISE/vme64xcore_top_reg_cs.ngc
Project.device.designOutputFile=/ohr/vme64x-core/trunk/HDL/VFC_ISE/vme64xcore_top_reg_cs.ngc
Project.device.deviceFamily=18
......@@ -7,25 +7,25 @@ Project.device.enableRPMs=true
Project.device.outputDirectory=/ohr/vme64x-core/trunk/HDL/VFC_ISE/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=
Project.filter<10>=*aM*OVERSAMPLED*
Project.filter<11>=*AS*Edge*
Project.filter<12>=*ASfallingEdge*
Project.filter<13>=*as_*
Project.filter<14>=*as*
Project.filter<15>=*oversampled*
Project.filter<16>=*AS*
Project.filter<17>=*CLK*
Project.filter<18>=*CLI*
Project.filter<1>=*LWORDinputSample*
Project.filter<2>=*LWORDinputSamplee*
Project.filter<3>=*ADDRinputSample*
Project.filter<4>=*AMinputSample*
Project.filter<5>=AM
Project.filter<6>=*clk*
Project.filter<7>=**
Project.filter<8>=*dtack*
Project.filter<9>=*aM*
Project.filter<0>=*m_ac*
Project.filter<10>=*s_DSlatch*
Project.filter<11>=*IACK*
Project.filter<12>=*s_reset*
Project.filter<13>=*rst*
Project.filter<14>=**
Project.filter<15>=*mainFSMstate*
Project.filter<16>=*state*
Project.filter<17>=*stat*
Project.filter<18>=*enable*
Project.filter<1>=*m_*
Project.filter<2>=*s_st*
Project.filter<3>=*st*
Project.filter<4>=*
Project.filter<5>=*func*
Project.filter<6>=*s_is_d64*
Project.filter<7>=*cyc*
Project.filter<8>=*s_cyc*
Project.filter<9>=*s_lockSel*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
......@@ -142,7 +142,7 @@ Project.unit<0>.dataChannel<99>=UUT/VME_bus_1/ADDRinputSample/reg_o<24>
Project.unit<0>.dataChannel<9>=UUT/VME_bus_1/s_VMEaddrLatched<9>
Project.unit<0>.dataDepth=16384
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=106
Project.unit<0>.dataPortWidth=148
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
......@@ -254,6 +254,54 @@ Project.unit<0>.triggerChannel<6><6>=UUT/VME_bus_1/ADDRinputSample/reg_o<5>
Project.unit<0>.triggerChannel<6><7>=UUT/VME_bus_1/ADDRinputSample/reg_o<6>
Project.unit<0>.triggerChannel<6><8>=UUT/VME_bus_1/ADDRinputSample/reg_o<7>
Project.unit<0>.triggerChannel<6><9>=UUT/VME_bus_1/ADDRinputSample/reg_o<8>
Project.unit<0>.triggerChannel<7><0>=UUT/VME_bus_1/s_funcMatch<7>
Project.unit<0>.triggerChannel<7><1>=UUT/VME_bus_1/s_funcMatch<6>
Project.unit<0>.triggerChannel<7><2>=UUT/VME_bus_1/s_funcMatch<5>
Project.unit<0>.triggerChannel<7><3>=UUT/VME_bus_1/s_funcMatch<4>
Project.unit<0>.triggerChannel<7><4>=UUT/VME_bus_1/s_funcMatch<3>
Project.unit<0>.triggerChannel<7><5>=UUT/VME_bus_1/s_funcMatch<2>
Project.unit<0>.triggerChannel<7><6>=UUT/VME_bus_1/s_funcMatch<1>
Project.unit<0>.triggerChannel<7><7>=UUT/VME_bus_1/s_funcMatch<0>
Project.unit<0>.triggerChannel<8><0>=UUT/VME_bus_1/s_AMmatch<7>
Project.unit<0>.triggerChannel<8><1>=UUT/VME_bus_1/s_AMmatch<6>
Project.unit<0>.triggerChannel<8><2>=UUT/VME_bus_1/s_AMmatch<5>
Project.unit<0>.triggerChannel<8><3>=UUT/VME_bus_1/s_AMmatch<4>
Project.unit<0>.triggerChannel<8><4>=UUT/VME_bus_1/s_AMmatch<3>
Project.unit<0>.triggerChannel<8><5>=UUT/VME_bus_1/s_AMmatch<2>
Project.unit<0>.triggerChannel<8><6>=UUT/VME_bus_1/s_AMmatch<1>
Project.unit<0>.triggerChannel<8><7>=UUT/VME_bus_1/s_AMmatch<0>
Project.unit<0>.triggerChannel<9><0>=UUT/VME_bus_1/s_lockSel
Project.unit<0>.triggerChannel<9><10>=UUT/VME_bus_1/s_cardSel
Project.unit<0>.triggerChannel<9><11>=UUT/VME_bus_1/s_dataDir
Project.unit<0>.triggerChannel<9><12>=UUT/VME_bus_1/s_dataOE
Project.unit<0>.triggerChannel<9><13>=UUT/VME_bus_1/s_dataPhase
Project.unit<0>.triggerChannel<9><14>=UUT/VME_bus_1/s_dataToAddrBus
Project.unit<0>.triggerChannel<9><15>=UUT/VME_bus_1/s_retry
Project.unit<0>.triggerChannel<9><16>=UUT/VME_bus_1/s_retry
Project.unit<0>.triggerChannel<9><17>=UUT/VME_bus_1/s_transferActive
Project.unit<0>.triggerChannel<9><18>=UUT/VME_bus_1/transfer_done_flag
Project.unit<0>.triggerChannel<9><19>=UUT/VME_bus_1/VME_BERR_o
Project.unit<0>.triggerChannel<9><1>=UUT/VME_bus_1/s_cardSel
Project.unit<0>.triggerChannel<9><20>=UUT/VME_bus_1/VME_DTACK_n_o
Project.unit<0>.triggerChannel<9><21>=UUT/VME_bus_1/VME_DTACK_OE_o
Project.unit<0>.triggerChannel<9><22>=UUT/VME_bus_1/VME_LWORD_n_b_o
Project.unit<0>.triggerChannel<9><23>=UUT/VME_bus_1/VME_RETRY_n_o
Project.unit<0>.triggerChannel<9><24>=ACK_i
Project.unit<0>.triggerChannel<9><25>=UUT/Uwb_dma/m_stb
Project.unit<0>.triggerChannel<9><26>=
Project.unit<0>.triggerChannel<9><27>=
Project.unit<0>.triggerChannel<9><28>=
Project.unit<0>.triggerChannel<9><29>=
Project.unit<0>.triggerChannel<9><2>=VME_RST_n_i_IBUF
Project.unit<0>.triggerChannel<9><30>=
Project.unit<0>.triggerChannel<9><31>=
Project.unit<0>.triggerChannel<9><3>=UUT/VME_bus_1/s_reset_s_mainFSMreset_OR_45_o
Project.unit<0>.triggerChannel<9><4>=UUT/VME_bus_1/s_reset_VME_IACKIN_n_oversampled_OR_47_o
Project.unit<0>.triggerChannel<9><5>=UUT/VME_bus_1/s_reset_VME_IACKIN_n_oversampled_OR_47_o
Project.unit<0>.triggerChannel<9><6>=UUT/VME_bus_1/s_DSlatch
Project.unit<0>.triggerChannel<9><7>=UUT/VME_bus_1/s_lockSel
Project.unit<0>.triggerChannel<9><8>=UUT/VME_bus_1/memReq_o
Project.unit<0>.triggerChannel<9><9>=UUT/VME_bus_1/s_berr
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCount<1>=1
......@@ -262,6 +310,9 @@ Project.unit<0>.triggerMatchCount<3>=1
Project.unit<0>.triggerMatchCount<4>=1
Project.unit<0>.triggerMatchCount<5>=1
Project.unit<0>.triggerMatchCount<6>=1
Project.unit<0>.triggerMatchCount<7>=1
Project.unit<0>.triggerMatchCount<8>=1
Project.unit<0>.triggerMatchCount<9>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchCountWidth<2><0>=0
......@@ -269,6 +320,9 @@ Project.unit<0>.triggerMatchCountWidth<3><0>=0
Project.unit<0>.triggerMatchCountWidth<4><0>=0
Project.unit<0>.triggerMatchCountWidth<5><0>=0
Project.unit<0>.triggerMatchCountWidth<6><0>=0
Project.unit<0>.triggerMatchCountWidth<7><0>=0
Project.unit<0>.triggerMatchCountWidth<8><0>=0
Project.unit<0>.triggerMatchCountWidth<9><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerMatchType<1><0>=1
Project.unit<0>.triggerMatchType<2><0>=1
......@@ -276,7 +330,10 @@ Project.unit<0>.triggerMatchType<3><0>=1
Project.unit<0>.triggerMatchType<4><0>=1
Project.unit<0>.triggerMatchType<5><0>=1
Project.unit<0>.triggerMatchType<6><0>=1
Project.unit<0>.triggerPortCount=7
Project.unit<0>.triggerMatchType<7><0>=1
Project.unit<0>.triggerMatchType<8><0>=1
Project.unit<0>.triggerMatchType<9><0>=1
Project.unit<0>.triggerPortCount=10
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortIsData<2>=true
......@@ -284,6 +341,9 @@ Project.unit<0>.triggerPortIsData<3>=true
Project.unit<0>.triggerPortIsData<4>=true
Project.unit<0>.triggerPortIsData<5>=true
Project.unit<0>.triggerPortIsData<6>=true
Project.unit<0>.triggerPortIsData<7>=true
Project.unit<0>.triggerPortIsData<8>=true
Project.unit<0>.triggerPortIsData<9>=true
Project.unit<0>.triggerPortWidth<0>=32
Project.unit<0>.triggerPortWidth<1>=6
Project.unit<0>.triggerPortWidth<2>=1
......@@ -291,6 +351,9 @@ Project.unit<0>.triggerPortWidth<3>=2
Project.unit<0>.triggerPortWidth<4>=32
Project.unit<0>.triggerPortWidth<5>=1
Project.unit<0>.triggerPortWidth<6>=32
Project.unit<0>.triggerPortWidth<7>=8
Project.unit<0>.triggerPortWidth<8>=8
Project.unit<0>.triggerPortWidth<9>=26
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
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