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VME64x core
Commit 9d52c5c1 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/rtl/platform/bridge_serdes_kintex7.vhd 0 → 100644
View file @ 9d52c5c1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity bridge_serdes_kintex7 is
generic (
g_mode : t_bridge_serdes_mode := MASTER;
g_SERDES_RX_DELAY_TAPS : integer := 0;
g_CLOCK_PERIOD : integer := 16;
g_use_idelay :boolean := false
);
port (
clk_125m_i : in std_logic := '0';
rst_n_i : in std_logic := '0';
bridge_d_i : in std_logic_vector(15 downto 0);
bridge_frame_i : in std_logic;
bridge_d_o : out std_logic_vector(15 downto 0);
bridge_frame_o : out std_logic;
bridge_clk_o : out std_logic;
bridge_rst_n_o : out std_logic;
ser_clk_p_i : in std_logic := '0';
ser_clk_n_i : in std_logic := '0';
ser_clk_p_o : out std_logic;
ser_clk_n_o : out std_logic;
ser_clk_p2_o : out std_logic;
ser_clk_n2_o : out std_logic;
ser_tx_o : out std_logic_vector(4 downto 0);
ser_rx_i : in std_logic_vector(4 downto 0)
);
end bridge_serdes_kintex7;
architecture rtl of bridge_serdes_kintex7 is
signal ser_clk_buf : std_logic;
signal clk_125m_0 : std_logic;
signal clk_500m_0 : std_logic;
signal clk_500m_180 : std_logic;
signal clk_iodelay_200m : std_logic;
signal pllout_clk_fb_pll, clk_fb_pll : std_logic;
signal pllout_clk_500m_0 : std_logic;
signal pllout_clk_iodelay_200m : std_logic;
signal pll_locked : std_logic;
type t_serdes_par_data is array(0 to 4) of std_logic_vector(3 downto 0);
signal ser_rx_predelay, ser_rx_postdelay : std_logic_vector(4 downto 0);
signal ser_tx_predelay, ser_tx_postdelay : std_logic_vector(4 downto 0);
signal par_rx, par_tx : t_serdes_par_data;
signal io_reset : std_logic;
signal ser_clk_out_prebuf : std_logic;
signal serdes_rx_bitslip : std_logic;
signal BITSLIP_cnt : unsigned(3 downto 0);
signal rst_cnt : unsigned(5 downto 0);
begin
p_reset : process(clk_125m_0)
begin
if rising_edge(clk_125m_0) then
if rst_n_i = '0' or pll_locked = '0' then
io_reset <= '1';
rst_cnt <= "111111";
else
if rst_cnt = 0 then
io_reset <= '0';
else
io_reset <= '1';
rst_cnt <= rst_cnt - 1;
end if;
end if;
end if;
end process;
clk_125m_0 <= clk_125m_i;
clk_500m_180 <= not clk_500m_0;
gen1 : if g_mode = MASTER generate
U_clk_buf : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
O => ser_clk_buf,
I => ser_clk_p_i,
IB => ser_clk_n_i
);
bridge_clk_o <= ser_clk_buf;
bridge_rst_n_o <= rst_n_i;
end generate gen1;
gen2 : if g_mode /= MASTER generate
ser_clk_buf <= clk_125m_i;
end generate gen2;
gen_clock_125m:if g_CLOCK_PERIOD = 8 generate
pll_iodelay_map : PLLE2_ADV
generic map(
BANDWIDTH => ("HIGH"),
COMPENSATION => ("ZHOLD"),
STARTUP_WAIT => ("FALSE"),
DIVCLK_DIVIDE => (1),
CLKFBOUT_MULT => (16),
CLKFBOUT_PHASE => (0.000),
CLKOUT0_DIVIDE => (10), -- 200 MHz
CLKOUT0_PHASE => (0.000),
CLKOUT0_DUTY_CYCLE => (0.500),
CLKOUT1_DIVIDE => (4), -- 500 MHz SDR
CLKOUT1_PHASE => (0.000),
CLKOUT1_DUTY_CYCLE => (0.500),
CLKIN1_PERIOD => (8.000))
port map(
CLKFBOUT => pllout_clk_fb_pll,
CLKOUT0 => pllout_clk_iodelay_200m,
CLKOUT1 => pllout_clk_500m_0,
-- Input clock control
CLKFBIN => clk_fb_pll,
CLKIN1 => ser_clk_buf,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
PWRDWN => '0',
RST => '0',
LOCKED => pll_locked
);
end generate gen_clock_125m;
gen_clock_62m5 : if g_CLOCK_PERIOD = 16 generate
pll_iodelay_map : PLLE2_ADV
generic map(
BANDWIDTH => ("HIGH"),
COMPENSATION => ("ZHOLD"),
STARTUP_WAIT => ("FALSE"),
DIVCLK_DIVIDE => (1),
CLKFBOUT_MULT => (16), -- VCO = 1000 MHz
CLKFBOUT_PHASE => (0.000),
CLKOUT0_DIVIDE => (5), -- 200 MHz
CLKOUT0_PHASE => (0.000),
CLKOUT0_DUTY_CYCLE => (0.500),
CLKOUT1_DIVIDE => (4), -- 250 MHz SDR
CLKOUT1_PHASE => (0.000),
CLKOUT1_DUTY_CYCLE => (0.500),
CLKIN1_PERIOD => (16.000))
port map(
CLKFBOUT => pllout_clk_fb_pll,
CLKOUT0 => pllout_clk_iodelay_200m,
CLKOUT1 => pllout_clk_500m_0,
-- Input clock control
CLKFBIN => clk_fb_pll,
CLKIN1 => ser_clk_buf,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
PWRDWN => '0',
RST => '0',
LOCKED => pll_locked
);
end generate gen_clock_62m5;
int_bufg : BUFG
port map (
O => clk_fb_pll,
I => pllout_clk_fb_pll
);
int2_bufg : BUFG
port map (
O => clk_500m_0,
I => pllout_clk_500m_0
);
int_bufg_clkiodelay : BUFG
port map (
O => clk_iodelay_200m,
I => pllout_clk_iodelay_200m
);
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => clk_iodelay_200m, -- 1-bit input: Reference clock input
RST => '0' -- 1-bit input: Active high reset input
);
gen_serdeses : for i in 0 to 4 generate
cmp_ibuf : IBUF
generic map (
IOSTANDARD => "SSTL15")
port map (
I => ser_rx_i(i),
O => ser_rx_predelay(i));
cmp_obuf : OBUF
generic map (
IOSTANDARD => "SSTL15")
port map (
O => ser_tx_o(i),
I => ser_tx_postdelay(i));
U_OSerdes : OSERDESE2
generic map (
DATA_RATE_OQ => "SDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => 4,
TRISTATE_WIDTH => 1,
SERDES_MODE => "MASTER")
port map (
D1 => par_tx(i)(3),
D2 => par_tx(i)(2),
D3 => par_tx(i)(1),
D4 => par_tx(i)(0),
D5 => '0',
D6 => '0',
D7 => '0',
D8 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
OCE => '1',
CLK => clk_500m_0,
CLKDIV => clk_125m_0,
OQ => ser_tx_postdelay(i),
TBYTEIN => '0',
TCE => '0',
RST => IO_RESET);
U_ISerdes : ISERDESE2
generic map (
DATA_RATE => "SDR",
DATA_WIDTH => 4,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "NONE",
SERDES_MODE => "MASTER")
port map (
Q1 => par_rx(i)(0),
Q2 => par_rx(i)(1),
Q3 => par_rx(i)(2),
Q4 => par_rx(i)(3),
BITSLIP => serdes_rx_bitslip,
CE1 => '1',
CE2 => '1',
clk => clk_500m_0,
clkb => clk_500m_180,
CLKDIV => clk_125m_0,
CLKDIVP => '0',
d => '0',
DDLY => ser_rx_postdelay(i),
rst => IO_RESET,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
ofb => '0',
oclk => '0',
oclkb => '0'
);
-- ser_tx_postdelay(i) <= '0';
gen_with_idelay : if g_use_idelay generate
U_Input_Delay: IDELAYE2
generic map (
-- CINVCTRL_SEL : string := "FALSE";
-- DELAY_SRC : string := "IDATAIN";
-- HIGH_PERFORMANCE_MODE : string := "FALSE";
-- IDELAY_TYPE : string := "FIXED";
-- IDELAY_VALUE : integer := 0;
-- IS_C_INVERTED : bit := '0';
-- IS_DATAIN_INVERTED : bit := '0';
-- IS_IDATAIN_INVERTED : bit := '0';
-- PIPE_SEL : string := "FALSE";
-- REFCLK_FREQUENCY : real := 200.0;
-- SIGNAL_PATTERN : string := "DATA"
CINVCTRL_SEL => "FALSE",
DELAY_SRC => "DATAIN",
HIGH_PERFORMANCE_MODE => "FALSE",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0, -- fixme
-- IS_C_INVERTED => '0',
-- IS_DATAIN_INVERTED => '0',
-- IS_IDATAIN_INVERTED => '0',
PIPE_SEL => "FALSE",
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA")
port map (
CNTVALUEOUT => open,
DATAOUT => ser_rx_postdelay(i),
C => clk_iodelay_200m,
CE => '1',
CINVCTRL => '0',
CNTVALUEIN => "00000",
DATAIN => ser_rx_predelay(i),
IDATAIN => '0',
INC => '0',
LD => '0',
LDPIPEEN => '0',
REGRST => IO_RESET);
end generate gen_with_idelay;
gen_without_idelay : if not g_use_idelay generate
ser_rx_postdelay(i) <= ser_rx_predelay(i);
end generate gen_without_idelay;
end generate gen_serdeses;
gen3 : if g_mode = SLAVE generate
OBUFDS_clk : OBUFDS
generic map (
IOSTANDARD => "DIFF_SSTL15",
SLEW => "FAST")
port map (
O => ser_clk_p_o,
OB => ser_clk_n_o,
I => ser_clk_out_prebuf);
U_OSerdes : OSERDESE2
generic map (
DATA_RATE_OQ => "SDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => 4,
TRISTATE_WIDTH => 1,
SERDES_MODE => "MASTER")
port map (
D1 => '0',
D2 => '0',
D3 => '1',
D4 => '1',
D5 => '0',
D6 => '0',
D7 => '0',
D8 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
OCE => '1',
CLK => clk_500m_0,
CLKDIV => clk_125m_0,
OQ => ser_clk_out_prebuf,
TBYTEIN => '0',
TCE => '0',
RST => IO_RESET);
-- ser_clk_out_prebuf <= '0';
end generate gen3;
gen_serdes_data : for i in 0 to 3 generate
par_tx(i)(0) <= bridge_d_i(i*4+0);
par_tx(i)(1) <= bridge_d_i(i*4+1);
par_tx(i)(2) <= bridge_d_i(i*4+2);
par_tx(i)(3) <= bridge_d_i(i*4+3);
bridge_d_o(i*4+0) <= par_rx(i)(0);
bridge_d_o(i*4+1) <= par_rx(i)(1);
bridge_d_o(i*4+2) <= par_rx(i)(2);
bridge_d_o(i*4+3) <= par_rx(i)(3);
bridge_frame_o <= par_rx(4)(0);
par_tx(4)(0) <= bridge_frame_i;
par_tx(4)(1) <= '0';
par_tx(4)(2) <= '0';
par_tx(4)(3) <= '0';
end generate gen_serdes_data;
p_serdes_bitslip : process(clk_125m_0, rst_n_i)
begin
if rst_n_i = '0' then
BITSLIP_cnt <= (others => '0');
serdes_rx_bitslip <= '0';
elsif rising_edge(clk_125m_0) then
if BITSLIP_cnt = 0 then
if par_rx(4) /= "0000" and par_rx(4) /= "0001" then
serdes_rx_bitslip <= '1';
BITSLIP_cnt <= to_unsigned(10, 4);
end if;
else
serdes_rx_bitslip <= '0';
BITSLIP_cnt <= BITSLIP_cnt - 1;
end if;
end if;
end process;
end rtl;
hdl/rtl/xvme64x_bridge_serdes.vhd 0 → 100644
View file @ 9d52c5c1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity xvme64x_bridge_serdes is
generic (
g_mode : t_bridge_serdes_mode := MASTER;
g_platform : string := "spartan6";
g_SERDES_RX_DELAY_TAPS : integer:= 0;
g_CLOCK_PERIOD : integer := 16
);
port (
clk_125m_i : in std_logic := '0';
rst_n_i : in std_logic := '0';
bridge_d_i : in std_logic_vector(15 downto 0);
bridge_frame_i : in std_logic;
bridge_d_o : out std_logic_vector(15 downto 0);
bridge_frame_o : out std_logic;
bridge_clk2_o : out std_logic;
bridge_clk_o : out std_logic;
bridge_rst_n_o : out std_logic;
ser_clk_p_i : in std_logic := '0';
ser_clk_n_i : in std_logic := '0';
ser_clk_p_o : out std_logic;
ser_clk_n_o : out std_logic;
ser_tx_o : out std_logic_vector(4 downto 0);
ser_rx_i : in std_logic_vector(4 downto 0)
);
end xvme64x_bridge_serdes;
architecture rtl of xvme64x_bridge_serdes is
begin
gen_platform_spartan6: if g_platform = "spartan6" generate
U_Wrapped_Serdes: entity work.bridge_serdes_spartan6
generic map (
g_mode => g_mode,
g_SERDES_RX_DELAY_TAPS => g_SERDES_RX_DELAY_TAPS,
g_CLOCK_PERIOD => g_CLOCK_PERIOD)
port map (
clk_125m_i => clk_125m_i,
rst_n_i => rst_n_i,
bridge_d_i => bridge_d_i,
bridge_frame_i => bridge_frame_i,
bridge_d_o => bridge_d_o,
bridge_frame_o => bridge_frame_o,
bridge_clk_o => bridge_clk_o,
bridge_clk2_o => bridge_clk2_o,
bridge_rst_n_o => bridge_rst_n_o,
ser_clk_p_i => ser_clk_p_i,
ser_clk_n_i => ser_clk_n_i,
ser_clk_p_o => ser_clk_p_o,
ser_clk_n_o => ser_clk_n_o,
ser_tx_o => ser_tx_o,
ser_rx_i => ser_rx_i
);
end generate gen_platform_spartan6;
gen_platform_kintex7: if g_platform = "kintex7" generate
U_Wrapped_Serdes: entity work.bridge_serdes_kintex7
generic map (
g_mode => g_mode,
g_SERDES_RX_DELAY_TAPS => g_SERDES_RX_DELAY_TAPS,
g_CLOCK_PERIOD => g_CLOCK_PERIOD)
port map (
clk_125m_i => clk_125m_i,
rst_n_i => rst_n_i,
bridge_d_i => bridge_d_i,
bridge_frame_i => bridge_frame_i,
bridge_d_o => bridge_d_o,
bridge_frame_o => bridge_frame_o,
bridge_clk_o => bridge_clk_o,
bridge_rst_n_o => bridge_rst_n_o,
ser_clk_p_i => ser_clk_p_i,
ser_clk_n_i => ser_clk_n_i,
ser_clk_p_o => ser_clk_p_o,
ser_clk_n_o => ser_clk_n_o,
ser_tx_o => ser_tx_o,
ser_rx_i => ser_rx_i);
end generate gen_platform_kintex7;
end rtl;
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