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VME64x core
Commits
9d52c5c1
Commit
9d52c5c1
authored
Dec 11, 2019
by
Tomasz Wlostowski
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bridge_serdes_kintex7.vhd
hdl/rtl/platform/bridge_serdes_kintex7.vhd
+470
-0
xvme64x_bridge_serdes.vhd
hdl/rtl/xvme64x_bridge_serdes.vhd
+102
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hdl/rtl/platform/bridge_serdes_kintex7.vhd
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hdl/rtl/xvme64x_bridge_serdes.vhd
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9d52c5c1
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
vme64x_pkg
.
all
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
entity
xvme64x_bridge_serdes
is
generic
(
g_mode
:
t_bridge_serdes_mode
:
=
MASTER
;
g_platform
:
string
:
=
"spartan6"
;
g_SERDES_RX_DELAY_TAPS
:
integer
:
=
0
;
g_CLOCK_PERIOD
:
integer
:
=
16
);
port
(
clk_125m_i
:
in
std_logic
:
=
'0'
;
rst_n_i
:
in
std_logic
:
=
'0'
;
bridge_d_i
:
in
std_logic_vector
(
15
downto
0
);
bridge_frame_i
:
in
std_logic
;
bridge_d_o
:
out
std_logic_vector
(
15
downto
0
);
bridge_frame_o
:
out
std_logic
;
bridge_clk2_o
:
out
std_logic
;
bridge_clk_o
:
out
std_logic
;
bridge_rst_n_o
:
out
std_logic
;
ser_clk_p_i
:
in
std_logic
:
=
'0'
;
ser_clk_n_i
:
in
std_logic
:
=
'0'
;
ser_clk_p_o
:
out
std_logic
;
ser_clk_n_o
:
out
std_logic
;
ser_tx_o
:
out
std_logic_vector
(
4
downto
0
);
ser_rx_i
:
in
std_logic_vector
(
4
downto
0
)
);
end
xvme64x_bridge_serdes
;
architecture
rtl
of
xvme64x_bridge_serdes
is
begin
gen_platform_spartan6
:
if
g_platform
=
"spartan6"
generate
U_Wrapped_Serdes
:
entity
work
.
bridge_serdes_spartan6
generic
map
(
g_mode
=>
g_mode
,
g_SERDES_RX_DELAY_TAPS
=>
g_SERDES_RX_DELAY_TAPS
,
g_CLOCK_PERIOD
=>
g_CLOCK_PERIOD
)
port
map
(
clk_125m_i
=>
clk_125m_i
,
rst_n_i
=>
rst_n_i
,
bridge_d_i
=>
bridge_d_i
,
bridge_frame_i
=>
bridge_frame_i
,
bridge_d_o
=>
bridge_d_o
,
bridge_frame_o
=>
bridge_frame_o
,
bridge_clk_o
=>
bridge_clk_o
,
bridge_clk2_o
=>
bridge_clk2_o
,
bridge_rst_n_o
=>
bridge_rst_n_o
,
ser_clk_p_i
=>
ser_clk_p_i
,
ser_clk_n_i
=>
ser_clk_n_i
,
ser_clk_p_o
=>
ser_clk_p_o
,
ser_clk_n_o
=>
ser_clk_n_o
,
ser_tx_o
=>
ser_tx_o
,
ser_rx_i
=>
ser_rx_i
);
end
generate
gen_platform_spartan6
;
gen_platform_kintex7
:
if
g_platform
=
"kintex7"
generate
U_Wrapped_Serdes
:
entity
work
.
bridge_serdes_kintex7
generic
map
(
g_mode
=>
g_mode
,
g_SERDES_RX_DELAY_TAPS
=>
g_SERDES_RX_DELAY_TAPS
,
g_CLOCK_PERIOD
=>
g_CLOCK_PERIOD
)
port
map
(
clk_125m_i
=>
clk_125m_i
,
rst_n_i
=>
rst_n_i
,
bridge_d_i
=>
bridge_d_i
,
bridge_frame_i
=>
bridge_frame_i
,
bridge_d_o
=>
bridge_d_o
,
bridge_frame_o
=>
bridge_frame_o
,
bridge_clk_o
=>
bridge_clk_o
,
bridge_rst_n_o
=>
bridge_rst_n_o
,
ser_clk_p_i
=>
ser_clk_p_i
,
ser_clk_n_i
=>
ser_clk_n_i
,
ser_clk_p_o
=>
ser_clk_p_o
,
ser_clk_n_o
=>
ser_clk_n_o
,
ser_tx_o
=>
ser_tx_o
,
ser_rx_i
=>
ser_rx_i
);
end
generate
gen_platform_kintex7
;
end
rtl
;
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