Commit 97beda2c authored by serrano's avatar serrano

First thoughts on IRQ controller

git-svn-id: 665b4545-5c6b-4c24-801b-41150b02b44b
parent 0076a275
......@@ -20,9 +20,36 @@ There are a number of outputs which are supposed to go to the outside
world (VME_DTACK_n_o, WE_o, VME_DATA_DIR_o...) and which are not using
I/O FFs because they are the result of some combinational logic. This
will result in tricky timing issues, and need complex constraints to
P&R to guarantee consistent results. I would strongly advice to make
P&R to guarantee consistent results. I would strongly advise to make
sure all these signals are outputs of I/O FFs, with any necessary
logic placed *before* these FFs.
logic placed *before* these FFs. In general, all inputs to the core
should be sampled before using them, and all outputs should be the
result of clocking in I/O FFs.
Text diagram in the initial comments not clear regarding state
Line 69: "To avoid the time constraint" -> "To respect the timing
Signal naming is not consistent. If the "s_" prefix is used, it should
be used for all internal signals.
Instantiation of many FlipFlopD components: a single clocked process
would be more compact and easier to understand.
Line 247: why should the interrupt controller not be allowed to go to
the IRQ state when VME_IACKIN_n_i='0'? That line could be at '0'
because of some other interrupt from another module in the
crate. Because the INT_Req input (shouldn't this be called INT_Req_i?)
is supposed to be a pulse, this can lead to interrupt requests being
- Check iack_in -> iack_out part.
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