Skip to content

V
VME64x core
Commit 8e54f7dc authored by palvarez's avatar palvarez
Browse files
Options 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@95 665b4545-5c6b-4c24-801b-41150b02b44b
parent 4f63d6c6
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 245 additions and 37 deletions
HDL/VFC_ISE/VME64e_VFC.gise
View file @ 8e54f7dc
......@@ -303,7 +303,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1309177095" xil_pn:in_ck="-4386731544833275205" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7631510052154532617" xil_pn:start_ts="1309177006">
<transform xil_pn:end_ts="1309356540" xil_pn:in_ck="-4386731544833275205" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7631510052154532617" xil_pn:start_ts="1309356449">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -326,7 +326,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1309275810" xil_pn:in_ck="1991227451224517426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5973292016675018579" xil_pn:start_ts="1309275796">
<transform xil_pn:end_ts="1309356681" xil_pn:in_ck="1991227451224517426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5973292016675018579" xil_pn:start_ts="1309356540">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -338,11 +338,9 @@
<outfile xil_pn:name="vme64xcore_top_reg_cs.ngc"/>
<outfile xil_pn:name="vme64xcore_top_reg_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1309275931" xil_pn:in_ck="-8441102077107081157" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1824173063049107586" xil_pn:start_ts="1309275810">
<transform xil_pn:end_ts="1309356865" xil_pn:in_ck="-8441102077107081157" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1824173063049107586" xil_pn:start_ts="1309356681">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.pcf"/>
<outfile xil_pn:name="vme64xcore_top_reg_map.map"/>
......@@ -353,7 +351,7 @@
<outfile xil_pn:name="vme64xcore_top_reg_summary.xml"/>
<outfile xil_pn:name="vme64xcore_top_reg_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1309276057" xil_pn:in_ck="3353801450926630214" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="2881300017542290041" xil_pn:start_ts="1309275931">
<transform xil_pn:end_ts="1309357049" xil_pn:in_ck="3353801450926630214" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="2881300017542290041" xil_pn:start_ts="1309356865">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -367,7 +365,7 @@
<outfile xil_pn:name="vme64xcore_top_reg_pad.txt"/>
<outfile xil_pn:name="vme64xcore_top_reg_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1309276985" xil_pn:in_ck="-6139244621610154419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="2321585675605421658" xil_pn:start_ts="1309276932">
<transform xil_pn:end_ts="1309357118" xil_pn:in_ck="-6139244621610154419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="2321585675605421658" xil_pn:start_ts="1309357049">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -409,7 +407,7 @@
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1309276057" xil_pn:in_ck="-6179112853177871454" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="5478904096812716945" xil_pn:start_ts="1309276038">
<transform xil_pn:end_ts="1309357049" xil_pn:in_ck="-6179112853177871454" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="5478904096812716945" xil_pn:start_ts="1309357026">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
HDL/VFC_ISE/VMEScope.cdc
View file @ 8e54f7dc
This diff is collapsed.
HDL/VFC_dev/vme64xcore_top_reg.vhd
View file @ 8e54f7dc
......@@ -175,7 +175,8 @@ architecture beh of vme64xcore_top_reg is
signal STB_o : STD_LOGIC;
signal WE_o : STD_LOGIC;
signal VME_BBSY_n, VME_IACKIN_n_i, VME_IACKOUT_n_o : std_logic;
signal we_ram : std_logic;
signal we_ram : std_logic;
-- signal FpLed_onb8_5 : std_logic;
-- signal VME_DTACK_OE_o:std_logic;
-- signal VME_DATA_DIR_o:std_logic;
......@@ -183,7 +184,8 @@ architecture beh of vme64xcore_top_reg is
-- signal VME_ADDR_DIR_o: std_logic;
-- signal VME_ADDR_OE_o:std_logic;
-- signal s_VME_DTACK_n : std_logic;
-- Add your code here ...
-- Add your code here ...
signal counter : unsigned(26 downto 0) := (others => '0');
begin
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment