platform: fix reset for the IOSERDES

87a162be · Tomasz Wlostowski · aad74ea2 · 87a162be
Commit 87a162be authored Sep 06, 2021 by Tomasz Wlostowski
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Showing with 168 additions and 22 deletions

bridge_serdes_spartan6.vhd hdl/rtl/platform/bridge_serdes_spartan6.vhd +168 -22

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--- a/hdl/rtl/platform/bridge_serdes_spartan6.vhd
+++ b/hdl/rtl/platform/bridge_serdes_spartan6.vhd
@@ -6,6 +6,8 @@ use work.vme64x_pkg.all;
 library unisim;
 use unisim.vcomponents.all;

+use work.gencores_pkg.all;
+
 entity bridge_serdes_spartan6 is
  generic (
    g_mode     : t_bridge_serdes_mode := MASTER;
@@ -34,7 +36,9 @@ entity bridge_serdes_spartan6 is
    ser_clk_n_o : out std_logic;

    ser_tx_o : out std_logic_vector(4 downto 0);
-    ser_rx_i : in  std_logic_vector(4 downto 0)
+    ser_rx_i : in  std_logic_vector(4 downto 0);
+
+    dbg_o : out std_logic_vector(31 downto 0)

    );

@@ -69,6 +73,137 @@ architecture rtl of bridge_serdes_spartan6 is

  signal BITSLIP_cnt : unsigned(3 downto 0);

+component BUFPLL is
+
+  generic(
+
+      DIVIDE        : integer := 1;    -- {1..8}
+      ENABLE_SYNC   : boolean := TRUE
+      );
+
+  port(
+      IOCLK        : out std_ulogic;
+      LOCK         : out std_ulogic;
+      SERDESSTROBE : out std_ulogic;
+
+      GCLK         : in  std_ulogic;
+      LOCKED       : in  std_ulogic;
+      PLLIN        : in  std_ulogic
+    );
+
+end component;
+
+
+component  ISERDES2 is
+    generic (
+      BITSLIP_ENABLE : boolean := FALSE;
+      DATA_RATE      : string := "SDR";
+      DATA_WIDTH     : integer := 1;
+      INTERFACE_TYPE : string := "NETWORKING";
+      SERDES_MODE    : string := "NONE"
+    );
+
+    port (
+      CFB0                 : out std_ulogic;
+      CFB1                 : out std_ulogic;
+      DFB                  : out std_ulogic;
+      FABRICOUT            : out std_ulogic;
+      INCDEC               : out std_ulogic;
+      Q1                   : out std_ulogic;
+      Q2                   : out std_ulogic;
+      Q3                   : out std_ulogic;
+      Q4                   : out std_ulogic;
+      SHIFTOUT             : out std_ulogic;
+      VALID                : out std_ulogic;
+      BITSLIP              : in std_ulogic := 'L';
+      CE0                  : in std_ulogic := 'H';
+      CLK0                 : in std_ulogic;
+      CLK1                 : in std_ulogic;
+      CLKDIV               : in std_ulogic;
+      D                    : in std_ulogic;
+      IOCE                 : in std_ulogic := 'H';
+      RST                  : in std_ulogic := 'L';
+      SHIFTIN              : in std_ulogic      
+    );
+    end component;
+
+    
+  component OSERDES2 is
+    generic (
+      BYPASS_GCLK_FF : boolean := FALSE;
+      DATA_RATE_OQ : string := "DDR";
+      DATA_RATE_OT : string := "DDR";
+      DATA_WIDTH : integer := 2;
+      OUTPUT_MODE : string := "SINGLE_ENDED";
+      SERDES_MODE : string := "NONE";
+      TRAIN_PATTERN : integer := 0
+    );
+
+    port (
+      OQ                   : out std_ulogic;
+      SHIFTOUT1            : out std_ulogic;
+      SHIFTOUT2            : out std_ulogic;
+      SHIFTOUT3            : out std_ulogic;
+      SHIFTOUT4            : out std_ulogic;
+      TQ                   : out std_ulogic;
+      CLK0                 : in std_ulogic;
+      CLK1                 : in std_ulogic;
+      CLKDIV               : in std_ulogic;
+      D1                   : in std_ulogic;
+      D2                   : in std_ulogic;
+      D3                   : in std_ulogic;
+      D4                   : in std_ulogic;
+      IOCE                 : in std_ulogic := 'H';
+      OCE                  : in std_ulogic := 'H';
+      RST                  : in std_ulogic;
+      SHIFTIN1             : in std_ulogic;
+      SHIFTIN2             : in std_ulogic;
+      SHIFTIN3             : in std_ulogic;
+      SHIFTIN4             : in std_ulogic;
+      T1                   : in std_ulogic;
+      T2                   : in std_ulogic;
+      T3                   : in std_ulogic;
+      T4                   : in std_ulogic;
+      TCE                  : in std_ulogic;
+      TRAIN                : in std_ulogic      
+    );
+  end component;
+
+  component IODELAY2 is
+    generic (
+      COUNTER_WRAPAROUND : string := "WRAPAROUND";
+      DATA_RATE : string := "SDR";
+      DELAY_SRC : string := "IO";
+      IDELAY2_VALUE : integer := 0;
+      IDELAY_MODE : string := "NORMAL";
+      IDELAY_TYPE : string := "DEFAULT";
+      IDELAY_VALUE : integer := 0;
+      ODELAY_VALUE : integer := 0;
+      SERDES_MODE : string := "NONE";
+      SIM_TAPDELAY_VALUE : integer := 75
+    );
+
+    port (
+      BUSY                 : out std_ulogic;
+      DATAOUT              : out std_ulogic;
+      DATAOUT2             : out std_ulogic;
+      DOUT                 : out std_ulogic;
+      TOUT                 : out std_ulogic;
+      CAL                  : in std_ulogic;
+      CE                   : in std_ulogic;
+      CLK                  : in std_ulogic;
+      IDATAIN              : in std_ulogic;
+      INC                  : in std_ulogic;
+      IOCLK0               : in std_ulogic;
+      IOCLK1               : in std_ulogic;
+      ODATAIN              : in std_ulogic;
+      RST                  : in std_ulogic;
+      T                    : in std_ulogic      
+    );
+    end component;
+
+
+  
 component chipscope_ila
    port (
      CONTROL : inout std_logic_vector(35 downto 0);
@@ -102,27 +237,27 @@ begin
  bridge_d_o <= bridge_d_out;
  bridge_frame_o <= bridge_frame_out;
  
-    chipscope_ila_1 : chipscope_ila
-    port map (
-      CONTROL => CONTROL,
-      CLK     => clk_125m_i,
-      TRIG0   => TRIG0,
-      TRIG1   => TRIG1,
-      TRIG2   => TRIG2,
-      TRIG3   => TRIG3);
-
-    trig0(0) <= bridge_frame_i;
-    trig0(16 downto 1) <= bridge_d_i;
-    trig1(0) <= bridge_frame_out;
-    trig1(16 downto 1) <= bridge_d_out;
-    trig2(0) <= rst_n_i;
-  trig3(7 downto 0) <= std_logic_vector(cnt);
-  trig3(15 downto 8) <= std_logic_vector(cnt2);
+  --   chipscope_ila_1 : chipscope_ila
+  --   port map (
+  --     CONTROL => CONTROL,
+  --     CLK     => clk_125m_i,
+  --     TRIG0   => TRIG0,
+  --     TRIG1   => TRIG1,
+  --     TRIG2   => TRIG2,
+  --     TRIG3   => TRIG3);
+
+  --   trig0(0) <= bridge_frame_i;
+  --   trig0(16 downto 1) <= bridge_d_i;
+  --   trig1(0) <= bridge_frame_out;
+  --   trig1(16 downto 1) <= bridge_d_out;
+  --   trig2(0) <= rst_n_i;
+  -- trig3(7 downto 0) <= std_logic_vector(cnt);
+  -- trig3(15 downto 8) <= std_logic_vector(cnt2);
  
  
-  chipscope_icon_1 : chipscope_icon
-    port map (
-      CONTROL0 => CONTROL);
+  -- chipscope_icon_1 : chipscope_icon
+  --   port map (
+  --     CONTROL0 => CONTROL);


  process(clk_125m_i)
@@ -159,7 +294,18 @@ begin
    bridge_clk2_o <= ser_clk_buf;
    
    bridge_clk_o <= clk_125m_0;
-    bridge_rst_n_o <= rst_n_i;
+--    bridge_rst_n_o <= rst_n_i;
+
+
+    U_Gen_Reset : gc_reset
+      generic map (
+        g_clocks    => 1)
+      port map (
+        free_clk_i => ser_clk_buf,
+        locked_i   => pll_locked,
+        clks_i(0) => clk_125m_0,
+        rstn_o(0) => bridge_rst_n_o);
+
    
  end generate gen1;

@@ -510,7 +656,7 @@ gen_clk_62m5 : if g_CLOCK_PERIOD = 16 generate
      end if;
    end if;
  end process;
-  
+
  
 end rtl;